Xilinx Floating-Point 浮點(diǎn)IP加減法的仿真驗(yàn)證案例

作者：OpenSLee

1、float IP的創(chuàng)建

搜索float雙擊Floating-point

1 > Operation Selection 我們這里選擇浮點(diǎn)數(shù)的加減法驗(yàn)證。

2 > Precision of Inputs 我們選擇單晶浮點(diǎn)數(shù)（Single）,指數(shù)位寬Exponent Width 8bit 尾數(shù)位寬24 bit

3 > Optimizations默認(rèn)值

4 > Interface Options Latency選擇1

2、浮點(diǎn)IP加減法的仿真驗(yàn)證

我們用python 自動(dòng)生成100000個(gè)隨機(jī)浮點(diǎn)數(shù)a和b以及a和b的相加或相減的結(jié)果。

python代碼(float32(a)+float32(b)=float32(c))：

import bitstring, random 
span = 10000000
iteration = 100000

def ieee754(flt):
    b = bitstring.BitArray(float=flt, length=32)
    return b

with open("TestAdd.txt", "w") as f:
    for i in range(iteration):
        a = ieee754(random.uniform(-span, span))
        b = ieee754(random.uniform(-span, span))
        ab = ieee754(a.float  + b.float)
        f.write(a.hex +"_" +  b.hex  +  "_" + ab.hex + "/n")

浮點(diǎn)數(shù)加法驗(yàn)證python結(jié)果（部分）：

4a953fc4_ca39838f_49e1f7f2
4b14900e_492290ab_4b1eb919
4aedbfc3_4b146c7e_4b85a630
ca4bb7f6_cb162f1d_cb491d1a
ca1ca77e_4ad19cc6_4a834907
c96e52c3_c9c7778d_ca1f5077
4ab9c1cc_cb187d76_ca6e7240
4b18508e_4a8e5556_4b5f7b39
cb103fa5_ca1765cf_cb361919
4a09db98_ca2feb0d_c9183dd4
ca626910_4a991e54_499fa730
c983aaa6_4b0534fd_4ae97f50
49e9e5f2_cad6005d_ca9b86e0
491b3266_4a3e2d28_4a64f9c2
ca935d66_caae8cbc_cb20f511
4a150544_4a645ebe_4abcb201

3、xilinx float IP的加法驗(yàn)證

s_axis_a_tdata,s_axis_b_tdata和m_axis_result_tdata分別代表浮點(diǎn)操作的a,b和結(jié)果c。

s_axis_operation_tdata的最低位為0時(shí)為加法，為1時(shí)為減法運(yùn)算。

m_axis_result_tvalid當(dāng)次信號(hào)為1時(shí)，結(jié)果有效。

浮點(diǎn)數(shù)加減法仿真頂層Float_AddSub_tb：

`timescale 1ns / 1ps
`define N_TESTS 100000
module Float_AddSub_tb();
    
 reg aclk;                           
 reg s_axis_a_tvalid;                
 wire s_axis_a_tready;               
 reg [31 : 0] s_axis_a_tdata;        
 reg s_axis_b_tvalid;                
 wire s_axis_b_tready;               
 reg [31 : 0] s_axis_b_tdata;        
 reg s_axis_operation_tvalid;        
 wire s_axis_operation_tready;       
 reg [7 : 0] s_axis_operation_tdata; 
 wire m_axis_result_tvalid;          
 reg m_axis_result_tready;           
 wire [31 : 0] m_axis_result_tdata;

reg [95:0] testVector [`N_TESTS-1:0];
reg test_stop;
reg [31:0] Expected_result;
reg [31:0] Expected_result_r;
integer mcd;
integer test_n;
integer pass;
integer error;

initial begin
  aclk = 0;
  test_n = 0;
  pass =0;
  error = 0;
  test_stop =0;
  s_axis_a_tvalid = 0;
  s_axis_b_tvalid = 0;
  Expected_result = 0;
  Expected_result_r = 0;
  s_axis_a_tdata = 0;
  s_axis_b_tdata = 0;
  s_axis_operation_tvalid = 1;
  s_axis_operation_tdata =8'b0000_0000;//Add
  //s_axis_operation_tdata =8'b0000_0001;//Sub
  m_axis_result_tready = 1;
  $readmemh("TestAdd.txt", testVector);//Add
  mcd = $fopen("ResultsAdd.txt");//Add
  
  //$readmemh("TestSub.txt", testVector);//Sub
 //mcd = $fopen("ResultsSub.txt");//Sub
  
  repeat(100000) begin
   #10 test_n = test_n + 1'b1;
  end
  
  wait(test_stop==1'b1)begin
    $fclose(mcd);
    $finish;
  end
end


always #(5) aclk = ~aclk;
  
  always @(posedge aclk) begin
    Expected_result_r  %d",test_n);
          pass = pass + 1'b1;
        end


      if ((m_axis_result_tvalid == 1) && (m_axis_result_tdata[31:11] != Expected_result_r[31:11]))
        begin
          $fdisplay (mcd,"Test Failed Expected Result = %h, Obtained s_axis_b_tdata = %h, Test Number -> %d",Expected_result,s_axis_b_tdata,test_n);
          error = error + 1'b1;
        end
      
      if (test_n >= `N_TESTS) 
      begin
        $fdisplay(mcd,"Completed %d tests, %d passed and %d fails.", test_n, pass, error);
        test_stop = 1'b1;
      end
  end    
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
floating_AddSUB your_instance_name (
  .aclk(aclk),                                        // input wire aclk
  .s_axis_a_tvalid(s_axis_a_tvalid),                  // input wire s_axis_a_tvalid
  .s_axis_a_tready(s_axis_a_tready),                  // output wire s_axis_a_tready
  .s_axis_a_tdata(s_axis_a_tdata),                    // input wire [31 : 0] s_axis_a_tdata
  .s_axis_b_tvalid(s_axis_b_tvalid),                  // input wire s_axis_b_tvalid
  .s_axis_b_tready(s_axis_b_tready),                  // output wire s_axis_b_tready
  .s_axis_b_tdata(s_axis_b_tdata),                    // input wire [31 : 0] s_axis_b_tdata
  .s_axis_operation_tvalid(s_axis_operation_tvalid),  // input wire s_axis_operation_tvalid
  .s_axis_operation_tready(s_axis_operation_tready),  // output wire s_axis_operation_tready
  .s_axis_operation_tdata(s_axis_operation_tdata),    // input wire [7 : 0] s_axis_operation_tdata
  .m_axis_result_tvalid(m_axis_result_tvalid),        // output wire m_axis_result_tvalid
  .m_axis_result_tready(m_axis_result_tready),        // input wire m_axis_result_tready
  .m_axis_result_tdata(m_axis_result_tdata)           // output wire [31 : 0] m_axis_result_tdata
);

endmodule

仿真結(jié)果：

Completed      100000 tests,       99999 passed and           0 fails.

通過(guò)仿真xilinx浮點(diǎn)ip的計(jì)算結(jié)果與python代碼的輸出結(jié)果一致，仿真成功。大家可以按照此方法仿真其他的算法中的計(jì)算公式或過(guò)程。首先利用C、matlab或者python等高級(jí)語(yǔ)言將算法的輸入和輸出一起打印出來(lái)，然后再讀入到verilog的算法模型里面，通過(guò)打印出計(jì)算結(jié)果或誤差來(lái)分析我們自己的算法的錯(cuò)誤或者誤差出現(xiàn)在哪里。

編輯：hfy