適用于H.264視頻解碼器的VLD設(shè)計

設(shè)計了一種適合于H.264 的變字長解碼器,根據(jù)碼流特點進行模塊劃分,減少硬件開銷;采用并行結(jié)構(gòu)解NAL 包,解碼效率高采用了桶形移位器進行并行解碼每個時鐘解一個碼字采用Verilog 語言進行設(shè)計仿真并通過了FPGA 驗證可以在FPGA 上實時解碼標準清晰度的H.264 視頻用0.18mm CMOS 工藝庫作綜合.電路規(guī)模為1.6 萬門左右,最高頻率能夠達到150MHz.
關(guān)鍵詞 專用集成電路 視頻解碼 變字 長解碼 H.264

Abstract This paper proposes an implementation of variable length decoder for H.264. The design is separated into several parts according to the specialty of the code flow so that the hardware cost can be decreased. The NAL packet is decoded by parallel structure module to get the high decoding efficiency. The barrel-shifters which are based on parallel structure can decode one code in every cycle. The module is designed , simulated based on Verilog HDL. The whole design has been verified by FPGA. The FPGA system can decode the standard-definition H.264 video in real-time. The design consists of 16k gates when synthesized based on 0.18mm CMOS library. The highest frequency can reach 150MHz.
Key words ASIC Video decoding Variable length decoding H.264