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電子發(fā)燒友網(wǎng)>電子資料下載>消費(fèi)電子>產(chǎn)品手冊(cè)>DS_K4B4G1646E-BY_Rev10-0三星DDR芯片手冊(cè)

DS_K4B4G1646E-BY_Rev10-0三星DDR芯片手冊(cè)

2017-07-18 | pdf | 1970KB | 次下載 | 1積分

資料介紹

三星DDR芯片手冊(cè)

  SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an “AS IS” basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners.

  DS_K4B4G1646E-BY_Rev10-0三星DDR芯片手冊(cè)

  The 4Gb DDR3 SDRAM E-die is organized as a 32Mbit x 16I/Os x 8banks, device. This synchronous device achieves high speed double-data-rate transfer rates of up to 1866Mb/sec/pin (DDR3-1866) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset 。 All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling)。 All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. The DDR3 device operates with a single 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V) power supply and 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V) VDDQ. The 4Gb DDR3L E-die device is available in 96ball FBGAs(x16).

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