Virtex-7 FPGA評估板VC707
The VC707 evaluation board for the Virtex®-7 FPGA provides a hardware environment for developing and evaluating designs targeting the Virtex-7 XC7VX485T-2FFG1761C FPGA. The VC707 board provides features common to many embedded processing systems, including a DDR3 SODIMM memory, an 8-lane PCI Express® interface, a tri-mode Ethernet PHY, general purpose I/O, and two UART interfaces. Other features can be added by using mezzanine cards attached to either of two VITA-57 FPGA mezzanine connectors (FMC) provided on the board. Two high pin count (HPC) FMCs are provided.
評估板VC707主要特性:
•Virtex-7 XC7VX485T-2FFG1761C FPGA
•1 GB DDR3 memory SODIMM
•128 MB Linear BPI Flash memory
•USB 2.0 ULPI Transceiver
•Secure Digital (SD) connector
•USB JTAG via Digilent module
•Clock Generation
•Fixed 200 MHz LVDS oscillator (differential)
•I2C programmable LVDS oscillator (differential)
•SMA connectors (differential)
•SMA connectors for GTX transceiver clocking
•GTX transceivers
•FMC1 HPC connector (eight GTX transceivers)
•FMC2 HPC connector (eight GTX transceiver)
•SMA connectors (one pair each for TX, RX and REFCLK)
•pCI Express (eight lanes)
•Small form-factor pluggable plus (SFP+) connector
•Ethernet PHY SGMII interface (RJ-45 connector)
•pCI Express endpoint connectivity
•Gen1 8-lane (x8)
•Gen2 8-lane (x8)
•SFP+ Connector
•10/100/1000 tri-speed Ethernet PHY
•USB-to-UART bridge
•HDMI codec
•I2C bus
•I2C MUX
•I2C EEPROM (1 KB)
•USER I2C programmable LVDS oscillator
•DDR3 SODIMM socket
•HDMI codec
•FMC1 HPC connector
•FMC2 HPC connector
•SFP+ connector
•I2C programmable jitter-attenuating precision clock multiplier
•Status LEDs
•Ethernet status
•power good
•FPGA INIT
•FPGA DONE
•User I/O
•USER LEDs (eight GPIO)
•User pushbuttons (five directional)
•CPU reset pushbutton
•User DIP switch (8-pole GPIO)
•User SMA GPIO connectors (one pair)
•LCD character display (16 characters x 2 lines)
•• Switches
•power on/off slide switch
•Configuration mode DIP switch
•VITA 57.1 FMC1 HPC Connector
•VITA 57.1 FMC2 HPC Connector
•power management
•pMBus voltage and current monitoring via TI power controller
•XADC header
•Configuration options
•Linear BPI Flash memory
•USB JTAG configuration port
•platform cable header JTAG configuration port
2012-4-1 14:52:47 上傳
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