ISA總線引腳定義
ISA 是 Industry Standard Architecture 的縮寫
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接口卡的外觀 |
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插槽的外觀 |
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引腳定義 |
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引腳 |
定義 |
方向 |
說明 |
|---|---|---|---|
|
A1 |
/I/O CH CK |
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A2 |
D7 |
Data bit 7 | |
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A3 |
D6 |
Data bit 6 | |
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A4 |
D5 |
Data bit 5 | |
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A5 |
D4 |
Data bit 4 | |
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A6 |
D3 |
Data bit 3 | |
|
A7 |
D2 |
Data bit 2 | |
|
A8 |
D1 |
Data bit 1 | |
|
A9 |
D0 |
Data bit 0 | |
|
A10 |
I/O CH RDY |
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|
A11 |
AEN |
Address enable; active high when DMA controls bus | |
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A12 |
A19 |
Address bit 19 | |
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A13 |
A18 |
Address bit 18 | |
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A14 |
A17 |
Address bit 17 | |
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A15 |
A16 |
Address bit 16 | |
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A16 |
A15 |
Address bit 15 | |
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A17 |
A14 |
Address bit 14 | |
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A18 |
A13 |
Address bit 13 | |
|
A19 |
A12 |
Address bit 12 | |
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A20 |
A11 |
Address bit 11 | |
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A21 |
A10 |
Address bit 10 | |
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A22 |
A9 |
Address bit 9 | |
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A23 |
A8 |
Address bit 8 | |
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A24 |
A7 |
Address bit 7 | |
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A25 |
A6 |
Address bit 6 | |
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A26 |
A5 |
Address bit 5 | |
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A27 |
A4 |
Address bit 4 | |
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A28 |
A3 |
Address bit 3 | |
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A29 |
A2 |
Address bit 2 | |
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A30 |
A1 |
Address bit 1 | |
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A31 |
A0 |
Address bit 0 | |
|
B1 |
GND |
|
Ground |
|
B2 |
RESET |
Active high to reset or initialize system logic | |
|
B3 |
+5V |
|
+5 VDC |
|
B4 |
IRQ2 |
Interrupt Request 2 | |
|
B5 |
-5VDC |
|
-5 VDC |
|
B6 |
DRQ2 |
DMA Request 2 | |
|
B7 |
-12VDC |
|
-12 VDC |
|
B8 |
/NOWS |
No WaitState | |
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B9 |
+12VDC |
|
+12 VDC |
|
B10 |
GND |
|
Ground |
|
B11 |
/SMEMW |
System Memory Write | |
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B12 |
/SMEMR |
System Memory Read | |
|
B13 |
/IOW |
I/O Write | |
|
B14 |
/IOR |
I/O Read | |
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B15 |
/DACK3 |
DMA Acknowledge 3 | |
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B16 |
DRQ3 |
DMA Request 3 | |
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B17 |
/DACK1 |
DMA Acknowledge 1 | |
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B18 |
DRQ1 |
DMA Request 1 | |
|
B19 |
/REFRESH |
Refresh | |
|
B20 |
CLOCK |
System Clock (67 ns, 8-8.33 MHz, 50% duty cycle) | |
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B21 |
IRQ7 |
Interrupt Request 7 | |
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B22 |
IRQ6 |
Interrupt Request 6 | |
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B23 |
IRQ5 |
Interrupt Request 5 | |
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B24 |
IRQ4 |
Interrupt Request 4 | |
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B25 |
IRQ3 |
Interrupt Request 3 | |
|
B26 |
/DACK2 |
DMA Acknowledge 2 | |
|
B27 |
T/C |
Terminal count; pulses high when DMA term. count reached | |
|
B28 |
ALE |
Address Latch Enable | |
|
B29 |
+5V |
|
+5 VDC |
|
B30 |
OSC |
High-speed Clock (70 ns, 14.31818 MHz, 50% duty cycle) | |
|
B31 |
GND |
|
Ground |
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|
|
C1 |
SBHE |
System bus high enable (data available on SD8-15) | |
|
C2 |
LA23 |
Address bit 23 | |
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C3 |
LA22 |
Address bit 22 | |
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C4 |
LA21 |
Address bit 21 | |
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C5 |
LA20 |
Address bit 20 | |
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C6 |
LA18 |
Address bit 19 | |
|
C7 |
LA17 |
Address bit 18 | |
|
C8 |
LA16 |
Address bit 17 | |
|
C9 |
/MEMR |
Memory Read (Active on all memory read cycles) | |
|
C10 |
/MEMW |
Memory Write (Active on all memory write cycles) | |
|
C11 |
SD08 |
Data bit 8 | |
|
C12 |
SD09 |
Data bit 9 | |
|
C13 |
SD10 |
Data bit 10 | |
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C14 |
SD11 |
Data bit 11 | |
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C15 |
SD12 |
Data bit 12 | |
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C16 |
SD13 |
Data bit 13 | |
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C17 |
SD14 |
Data bit 14 | |
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C18 |
SD15 |
Data bit 15 | |
|
D1 |
/MEMCS16 |
Memory 16-bit chip select (1 wait, 16-bit memory cycle) | |
|
D2 |
/IOCS16 |
I/O 16-bit chip select (1 wait, 16-bit I/O cycle) | |
|
D3 |
IRQ10 |
Interrupt Request 10 | |
|
D4 |
IRQ11 |
Interrupt Request 11 | |
|
D5 |
IRQ12 |
Interrupt Request 12 | |
|
D6 |
IRQ15 |
Interrupt Request 15 | |
|
D7 |
IRQ14 |
Interrupt Request 14 | |
|
D8 |
/DACK0 |
DMA Acknowledge 0 | |
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D9 |
DRQ0 |
DMA Request 0 | |
|
D10 |
/DACK5 |
DMA Acknowledge 5 | |
|
D11 |
DRQ5 |
DMA Request 5 | |
|
D12 |
/DACK6 |
DMA Acknowledge 6 | |
|
D13 |
DRQ6 |
DMA Request 6 | |
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D14 |
/DACK7 |
DMA Acknowledge 7 | |
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D15 |
DRQ7 |
DMA Request 7 | |
|
D16 |
+5 V |
|
|
|
D17 |
/MASTER |
Used with DRQ to gain control of system | |
|
D18 |
GND |
|
Ground |