DS26303短程線路接口單元與IDT82V2048的比較

摘要：本文比較了DS26303和IDT82V2048的不同，特別說(shuō)明了如何在已有的IDT82V2048應(yīng)用中使用DS26303，詳細(xì)闡述了它們的特性區(qū)別、寄存器和硬件設(shè)計(jì)時(shí)的考慮。

概述

本文比較了DS26303和IDT82V2048的不同，特別闡述了如何在已有的IDT82V2048應(yīng)用中使用DS26303。DS26303是一個(gè)單3.3V供電的8通道E1/T1/J1短程線路接口單元(LIU)。不需要更改軟件就可以支持IDT82V2048的功能，并提供附加的特性。不需要改變PCB，DS26303就可以用在現(xiàn)有的IDT82V2048應(yīng)用中，僅僅需要根據(jù)應(yīng)用改變外圍元器件值。

特性的區(qū)別分為三個(gè)不同部分：表1為DS26303具備而IDT82V2048不具備的一些特性；表2為IDT82V2048具備而DS26303不具備的一些特性。表3為DS26303和IDT82V2048共有但是在兩個(gè)器件上實(shí)現(xiàn)不同的特性。

表6到表10為DS26303和IDT82V2048寄存器之間的不同以及DS26303附加寄存器組提供的附加功能。圖1和表11為在現(xiàn)有的IDT82V2048應(yīng)用中使用DS26303時(shí)需要對(duì)器件值所做的細(xì)微改變。

表1. DS26303不同于IDT82V2048的特性

DS26303	IDT82V2048
Programmable option to clear interrupt status on write or read. Clear on read is default.	Not supported.
Individual channel control for jitter attenuator: Enable/disable FIFO depth FIFO limit trip	All channels have global control.
Internal software-selectable transmit and receive-side termination for 100Ω T1 twisted-pair, 110Ω J1 twisted-pair, 120Ω E1 twisted-pair, and 75Ω E1 coaxial applications.	Not supported.
In HPS mode, the transmitter output and the internal impedance of the receiver can be turned off with only the OE pin.	Requires that both receivers use the same front-end termination.
Built in BERT tester for diagnostics.	Not supported.
Individual channel control for: Short-circuit protection AIS enable on LOS RCLK inversion TCLK inversion	All channels have global control.
Individual channel-line violation detection.	Not supported.
Flexible MCLK See Table 4 for available input frequencies.	Not supported.
Programmable TECLK output pin (1.544MHz or 2.048MHz)	Not supported.
Programmable CLKA output pin See Table 5 for available output frequencies.	Not supported.
Flexible interrupt pin	Not supported.

表2. IDT82V2048不同于DS26303的特性

DS26303	IDT82V2048
Uses single optimal value.	Capability to select the jitter attenuator bandwidth.
Not provided.	Inband loopack (loopup and loopdown codes).
MLCK Pin Functionality The DS26303 and IDT82V2048 both require MCLK to for data with clock recovery as well as AIS detection. The MCLK pin of the IDT82V2048 provides additional functionality not present in the DS26303. IDT82V2048 MCLK held high. The IDT82V2048 slices the incoming bipolar line signal into RZ pulse (data-recovery mode). IDT82V2048 MCLK held low. All the receivers are powered down, and the output pins RCLKn, RDPn, and RDNn are switched to high impedance. Note that wait state generation through RDY/ACK is not available if MCLK is not provided.

表3. DS26303和IDT82V2048的特性區(qū)別

DS26303	IDT82V2048
3.3V LIU power only, 5V not provided.	5V LIU power.
Non-mux Intel? write address to WRB rising-edge setup time is 17ns.	Non-mux Intel write address to WRB rising-edge setup time is 6ns.
Expects non-mux Intel read address to be valid when RDB is active.	Non-mux Intel read address to RDB rising-edge setup time is 6ns. This might be an error in data sheet because data is out before this setup time.
Inactive RDY to tri-state delay time 12ns (max).	Inactive RDY to tri-state delay time 3ns (max).
Clears the interrupt pin when reading or writing the interrupt status.	Clear interrupt pin by reading the corresponding status register.
Jitter attenuator FIFO depths of 32 bits or 128 bits.	Jitter attenuator FIFO depths of 32 bits or 64 bits.
Individual channel control for jitter attenuator: Enable/disable FIFO depth FIFO limit trip	All channels have global control.

表4. DS26303 MCLK的選擇范圍

PLLE	MPS1, MPS0	MCLK MHz (±50ppm)	FREQS	T1 or E1 Mode
0	xx	1.544	x	T1
0	xx	2.048	x	E1
1	00	1.544	1	T1/J1 or E1
1	01	3.088	1	T1/J1 or E1
1	10	6.176	1	T1/J1 or E1
1	11	12.352	1	T1/J1 or E1
1	00	2.048	0	T1/J1 or E1
1	01	4.096	0	T1/J1 or E1
1	10	8.192	0	T1/J1 or E1
1	11	16.384	0	T1/J1 or E1

表5. DS26303時(shí)鐘A的選擇范圍

CLKA3 to CLKA0	MCLK (Hz)
0000	2.048M
0001	4.096M
0010	8.192M
0011	16.384M
0100	1.544M
0101	3.088M
0110	6.176M
0111	12.352M
1000	1.536M
1001	3.072M
1010	6.144M
1011	12.288M
1100	32k
1101	64k
1110	128k
1111	256k

寄存器的考慮事項(xiàng)

DS26303包括四個(gè)主要的寄存器組。

• 主寄存器組(DS26303和IDT82V2048)
• 二級(jí)寄存器組(DS26303和IDT82V2048)
• 獨(dú)立LIU寄存器組(DS26303獨(dú)有)
• BERT寄存器組(DS26303獨(dú)有)

為了利用DS26303的附加特性和靈活性，必須在IDT82V2048應(yīng)用的源代碼中添加程序。地址指針控制寄存器(ADDP)的地址為1Fh，它被用作指針來(lái)訪問(wèn)不同的寄存器組。表6給出了DS26303寄存器組列表和訪問(wèn)這些寄存器組時(shí)所需要的ADDP值。

表6. DS26303地址指針選擇

ADDP7 to ADDP0 (Hex)	Bank Name	DS26303	IDT82V2048
00	Primary Bank	Yes	Yes
AA	Secondary Bank	Yes	Yes
01	Individual LIU Bank	Yes	No
02	BERT Bank	Yes	No

DS26303的主寄存器組和IDT82V2048是一樣的。如果使用DS26303替換現(xiàn)有的IDT82V2048，并且僅用到主寄存器組，則不需要修改應(yīng)用軟件。表7給出了主寄存器組列表。

表7. DS26303和IDT82V2048的主寄存器組

Address (Hex)	DS26303 and IDT82V2048
00–15	Primary Registers
16–1E	Reserved
1F	ADDP

盡管DS26303與IDT82V2048都提供二級(jí)寄存器組，但并不是所有寄存器及其相應(yīng)功能都是一樣的。表8給出了二級(jí)寄存器組包含的寄存器列表，以及它們?cè)贒S26303和IDT82V2048中實(shí)現(xiàn)的功能。

DS26303包含另外兩個(gè)寄存器組：獨(dú)立LIU寄存器組和BERT寄存器組。表9為獨(dú)立LIU寄存器組包含的寄存器列表，表10為BERT寄存器組包含的寄存器列表。為了利用DS26303的附加特性和靈活性，必須在IDT82V2048應(yīng)用的源代碼中添加程序。

表8. DS26303的二級(jí)寄存器組

Address (Hex)	Register Name	DS26303	IDT82V2048
00	Single-Rail Mode Select	Yes	Yes
01	Line-Code Selection	Yes	Yes
02	Clock-Recovery Enable	No	Yes
03	Receiver Power-Down Enable	Yes	Yes
04	Transmitter Power-Down Enable	Yes	Yes
05	Excessive Zero-Detect Enable	Yes	Yes
06	Code-Violation-Detect Enable Bar	Yes	Yes
07	Receive Equalizer Enable	No	Yes
08	Inband Loopback (LB) Configuration	No	Yes
09	Inband LB Activation Code	No	Yes
0A	Inband LB Deactivation Code	No	Yes
0B	Inband LB Receive Status	No	Yes
0C	Inband LB Interrupt Mask	No	Yes
0D	Inband LB Interrupt Status	No	Yes
0E	Inband LB Activation/Deactivation Code Generator	No	Yes
1F	Set to AAh for access to Secondary Register Bank	Yes	Yes

表9. DS26303的獨(dú)立LIU寄存器組

Address (Hex)	Register Name
00	Individual JA Enable
01	Individual JA Position Select
02	Individual JA FIFO Depth Select
03	Individual JA FIFO Limit Trip
04	Individual Short-Circuit Protection Disable
05	Individual AIS Select
06	Master-Clock Select
07	Global-Management Register
08–0F	Reserved
10	Bit-Error-Rate Tester Control Register
12	Line-Violation Detect Status
13	Receive-Clock Invert
14	Transmit-Clock Invert
15	Clock-Control Register
16	RCLK Disable Upon LOS Register
1E	Global-Interrupt Status Control
1F	Set to 01h for access to Individual LIU Register Bank

表10. DS26303的BERT寄存器組

Address (Hex)	Register Name
00	BERT Control Register
01	Reserved
02	BERT Pattern Configuration 1
03	BERT Pattern Configuration 2
04	BERT Seed/Pattern 1
05	BERT Seed/Pattern 2
06	BERT Seed/Pattern 3
07	BERT Seed/Pattern 4
08	Transmit-Error Insertion Control
09–0A	Reserved
0C	BERT Status Register
0D	Reserved
0E	BERT Status Register Latched
10	BERT Status Register Interrupt Enable
11–13	Reserved
14	Receive Bit-Error Count Register 1
15	Receive Bit-Error Count Register 2
16	Receive Bit-Error Count Register 3
17	Receive Bit-Error Count Register 4
18	Receive Bit-Count Register 1
19	Receive Bit-Count Register 2
1A	Receive Bit-Count Register 3
1B	Receive Bit-Count Register 4
1C–1E	Reserved
1F	Set to 02h for access to BERT Register Bank

硬件考慮事項(xiàng)

不用改變PCB就可以用DS26303替換現(xiàn)有應(yīng)用中的IDT82V2048。需要做的是根據(jù)目標(biāo)應(yīng)用改變外部器件值。圖1為DS26303推薦的網(wǎng)絡(luò)端接電路，表11為DS26303正確端接時(shí)需要的器件值。

發(fā)送器

IDT82V2048要求發(fā)送端電阻串聯(lián)接入TTIP和TRING輸出，建議這些電阻應(yīng)該為0Ω (T1 3.3V模式)，9.5Ω (E1 75Ω同軸)或者9.1Ω (E1 120Ω雙絞線)。DS26303不要求電阻，所以所有模式中的電阻都應(yīng)該為0Ω。

接收器

在接收側(cè)，IDT82V2048要求端接阻抗為12.4Ω (T1 3.3V模式)，9.31Ω (E1 75Ω同軸)或者15Ω (E1 120Ω雙絞線)。當(dāng)使用外部阻抗模式時(shí)，DS26303的所有情況都要求用15Ω端接電阻；當(dāng)使用DS26303的軟件選取阻抗匹配模式，不需要任何電阻。IDT82V2048要求使用1kΩ電阻同RTIP和RRING管腳串聯(lián)。如果DS26303采用軟件選取端接/阻抗匹配模式，這些1kΩ的電阻可以用0Ω電阻代替。


圖1. LIU前端電路圖

表11. LIU前端值

Mode	Component	75Ω Coaxial	120Ω Twisted Pair	100Ω/110Ω Twisted Pair
Tx Capacitance	Ct	560pF (typ). Adjust for board parasitics for optimal return loss.
Tx Protection	Dt	International Rectifier: 11DQ04 or 10BQ060 Motorola: MBR0540T1
Rx Transformer 1:2	TFr	Pulse: T1124 (0°C to +70°C)
Tx Transformer 1:2	TFt	Pulse: T1114 (-40°C to +85°C)
Tx Decoupling (ATVDD)	C1	Common decoupling for all eight channels is 68μF.
Tx Decoupling (ATVDD)	C2	Recommended decoupling per channel is 0.1μF.
Rx Decoupling (AVDDn)	C3	Common decoupling for all eight channels is 68μF.
Rx Decoupling (AVDDn)	C4	Common decoupling for all eight channels is 0.1μF.
Rx Termination	C5	When in external impedance mode, Rx capacitance for all eight channels is 0.1μF. Do not populate if using internal impedance mode.
Rx Termination	Rt	When in external impedance mode, the two resistors for all modes shall be 15.0Ω ±1%. Do not populate if using internal impedance mode.
Voltage Protection	TVS1	SGS-Thomson: SMLVT 3V3 (3.3V transient suppressor)

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