• ADAU1361
• ADAU1461
• ADAU1761
• ADAU1961

• CN0219
• CN0296

• EVAL-ADAU1361Z
• EVAL-ADAU1761Z

The I2C device id depends on the ADDR0 and ADDR1 pin settings and needs to be set according to your board setup.

In this example we assume ADDR0=0 and ADDR1=0.

static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
?
	[--snip--]
	{
		I2C_BOARD_INFO("adau1761", 0x38),
	},
	[--snip--]
}

static int __init stamp_init(void)
{
	[--snip--]
	i2c_register_board_info(0, bfin_i2c_board_info,
				ARRAY_SIZE(bfin_i2c_board_info));
	[--snip--]
?
	return 0;
}
arch_initcall(board_init);

The ADAU1761 features one PLL:

enum adau17x1_pll {
    ADAU17X1_PLL
};

The PLL input signal is the MCLK signal.

enum adau17x1_pll_src {
    ADAU17X1_PLL_SRC_MCLK,
};

(The input frequency must configured to be between 8000000 and 27000000 Hz (8MHz - 27MHz). The output frequency must be configured to be between 45158000 and 49152000. Configuring the PLL with other input or output frequency will fail.)

The PLL runs at 1024 times the base sample rate. So for a 48000 Hz based sample rate you'd normally choose 49152000 Hz for the PLL output frequncey and for a 44100 Hz based sample rate 45158400 Hz.

The codec driver registers one DAI: adau-hifi

The DAIs can either use the PLL or the MCLK signal as source.

When using the PLL the DAIs rate should be set to the rate of the PLL. When using MCLK the rate should be set to frequency of the external MCLK signal.

enum adau17x1_clk_src {
    ADAU17X1_CLK_SRC_MCLK,
    ADAU17X1_CLK_SRC_PLL,
};

static int bfin_eval_adau1x61_hw_params(struct snd_pcm_substream *substream,
	struct snd_pcm_hw_params *params)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
	struct snd_soc_dai *codec_dai = rtd->codec_dai;
	int pll_rate;
	int ret;
?
	ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
			SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
	if (ret)
		return ret;
?
	ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
			SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
	if (ret)
		return ret;
?
	switch (params_rate(params)) {
	case 48000:
	case 8000:
	case 12000:
	case 16000:
	case 24000:
	case 32000:
	case 96000:
		pll_rate = 48000 * 1024;
		break;
	case 44100:
	case 7350:
	case 11025:
	case 14700:
	case 22050:
	case 29400:
	case 88200:
		pll_rate = 44100 * 1024;
		break;
	default:
		return -EINVAL;
	}
?
	ret = snd_soc_dai_set_pll(codec_dai, ADAU17X1_PLL,
			ADAU17X1_PLL_SRC_MCLK, 12288000, pll_rate);
	if (ret)
		return ret;
?
	ret = snd_soc_dai_set_sysclk(codec_dai, ADAU17X1_CLK_SRC_PLL, pll_rate,
			SND_SOC_CLOCK_IN);
?
	return ret;
}
?
?
static struct snd_soc_ops bfin_eval_adau1x61_ops = {
	.hw_params = bfin_eval_adau1x61_hw_params,
};
?
static struct snd_soc_dai_link bfin_eval_adau1x61_dai = {
	.name = "adau1x61",
	.stream_name = "ADAU1X61", 
	.cpu_dai_name = "bfin-i2s.0", 
	.codec_dai_name = "adau-hifi",
	.platform_name = "bfin-i2s-pcm-audio",
	.codec_name = "adau1761.0-0038",
	.ops = &bfin_eval_adau1x61_ops,
};

The ADAU1361 and ADAU1761 chips have basic TDM support.

• The number of slots can be either 2, 4 or 8 (ADAU1761 only).
• The slot width can be 32 (ADAU1361 only), 64, 48, 128 or 256 (ADAU1761 only)
• The slot mask must be either 0x03 (slot 0 and 1), 0x0c (slot 2 and 3), 0x30 (slot 4 and 5), 0xc0 (slot 6 and 7)

Example TDM configuration:

	ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x30, 0x0c, 8, 64);

In order to use the SigmaDSP core of the ADAU1761 you need to provide a firmware file. Please refer to the SigmaDSP Firmware Utility for Linux page on how to generate a firmware file. The firmware file for ADAU1761 driver has to be named adau1761.bin.

There is no dedicated Blackfin STAMP evaluation board for the ADAU1361 or ADAU1761. During test and driver development we used the EVAL-ADAU1361Z and EVAL-ADAU1761Z boards.

It can be easily wired to the Blackfin STAMP SPORT header.

Device Drivers  --->
[*] I2C support  --->
[*]   I2C Hardware Bus support  --->
***     I2C system bus drivers (mostly embedded / system-on-chip) ***
<*>       Blackfin TWI I2C support
(100)     Blackfin TWI I2C clock (kHz)

Enable ALSA SoC evaluation board driver:

Device Drivers  --->
 Sound card support  --->
   Advanced Linux Sound Architecture  --->
     ALSA for SoC audio support  --->
       Support for the EVAL-ADAU1X61 boards on Blackfin eval boards

Connect the STAMP SPORT 0 port (P6) to the EVAL-ADAU1X61 J1 and J6 headers.

Note that the SPORT has separate signals for the capture and playback clocks, while the ADAU1361 uses the same clock signals for both, so the EVAL-ADAU1X61 clock signal pins need to be connected to two STAMP pins each.

Load the driver and make sure the sound card is properly instantiated.

root:/> modprobe snd-bf5xx-i2s
root:/> modprobe snd-soc-bf5xx-i2s
root:/> modprobe snd-soc-adau1761
root:/> modprobe snd-soc-bfin-eval-adau1x61
bfin-i2s bfin-i2s.0: dma rx:3 tx:4, err irq:45, regs:ffc00800
dma_alloc_init: dma_page @ 0x02791000 - 256 pages at 0x03f00000
asoc: adau-hifi <-> bfin-i2s.0 mapping ok
ALSA device list:
  #0: bfin-eval-adau1x61

root:/> modprobe snd-pcm-oss
root:/> tone
TONE: generating sine wave at 1000 Hz...

root:/> arecord -f cd | aplay
Recording WAVE 'stdin' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo
Playing WAVE 'stdin' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo

• SigmaStudio
• SigmaDSP Firmware Utility for Linux
• SigmaStudio Network Utility for Linux