2.5Gb/s 16:1 復用器電路設計

本文采用0.18μm CMOS工藝設計了用于2.5Gb/s收發(fā)器系統(tǒng)的16:1復用器電路。該電路采用數(shù)?；旌系姆椒ㄟM行設計，第一級用數(shù)字電路實現(xiàn)16:4的復用，第二級用模擬電路實現(xiàn)4:1的復用，從而實現(xiàn)16:1的復用器。該電路采用SMIC 0.18μm工藝模型，使用Virtuoso AMS Simulator 工具進行了仿真。仿真結果表明，當電源電壓為1.8V，溫度范圍為0～70℃時，電路可以工作在2.5b/s，功耗約為6mW。
關鍵詞：收發(fā)器；復用器；數(shù)模混合

2.5Gb/s 16:1 Multiplexer Circuit Design Xing Li-dong1,2, Jiang Lin1 (1.Department of Computer Science, Xi’an University of Post & Telecommunications, Xi’an, 710061,China;
2.School of microelectronics ,Xidian University,Xi’an,710071,China) Abstract: A 16:1 multiplexer for 2.5Gb/s transceiver system designed with 0.18μm CMOS technology is presented in this paper. The circuit is designed with digital/analog mixed-signal methodology. The first level is realized with digital circuit for the 16:4 multiplexer , and the second level realize the 4:1 multiplexer by analog circuit. The circuit is simulated with SMIC 0.18μm CMOS model by Virtuoso AMS Simulator. It is shown that the circuit can run at a high speed of 2.5Gb/s under a 1.8V power supply and the temperature is between 0~70℃. Its power dissipation is about 6mW.
Key words: transceiver; multiplexer; digital/analog mixed-signal