帶DPGA的雙路8位A D轉(zhuǎn)換器的演示板TDA8798HL的

1. MAIN FEATURES OF THE TDA8798HL: ........................................................................................5
2. PRINCIPLE AND DESCRIPTION OF THE BOARD: ......................................................................8
3. OVERVIEW OF THE BOARD:.......................................................................................................... 10
4. PCB DESIGN:.................................................................................................................................... 13
4.1 MICROSTRIP LINES: ........................................................................................................................... 14
4.2 POWER SUPPLY WIRE:................................................................................................................. 14
4.3 ANALOG AND DIGITAL RETURN GROUND POINT:................................................................. 14
5. SPECIAL FEATURES OF THE APPLICATION BOARD:............................................................. 15
5.1 DPGA ANALOG INPUTS VIN1: .................................................................................................... 15
5.2 EXTERNAL FILTER:...................................................................................................................... 16
5.3 ADC ANALOG INPUTS BUF1 AND BUF1N: .................................................................................. 18
5.4 DATA OUTPUT A0 TO A7:............................................................................................................ 18
5.5 ADC ANALOG, DIGITAL AND OUTPUT STAGES POWER SUPPLY:................................................... 19
6. ENVIRONMENT CIRCUITS:........................................................................................................... 20
6.1 GENERAL POWER SUPPLY: .................................................................................................................. 20
6.2 EXTERNAL CLOCK SELECTOR: ................................................................................................. 21
6.3 D-TYPE FLIP-FLOP INTERFACE:................................................................................................... 22
6.4 MANUAL INTERFACE:................................................................................................................. 23
6.5 MULTIPLEXER: ............................................................................................................................. 25
7. OPERATING MODE:........................................................................................................................ 26
7.1 INPUT OPERATION:..................................................................................................................... 26
7.2 SINGLE CLOCK MODE:................................................................................................................ 27
7.3 DUAL CLOCK MODE:................................................................................................................... 28
7.4 DPGA MANUAL PROGRAMMATION (MODE 0 ONLY):............................................................. 29
7.5 DPGA DEMOBOARD/PC INTERFACE SOFTWARE (MODE 0 ONLY):...................................................... 30
7.6 QUICKVIEW OF THE DEMOBOARD:.......................................................................................... 34
8. PERFORMANCES:........................................................................................................................... 35
8.1 DEFINITION OF THE MEASURING PARAMETERS: .................................................................. 35
8.2 MEASUREMENT OF THE ADC 1 (MODE 1):............................................................................... 38
8.3 MEASUREMENT OF CHANNEL 1 (MODE 0) IN MINIMUM GAIN: .............................................. 39
8.4 MEASUREMENT OF CHANNEL 1 (MODE 0) IN MAXIMUM GAIN:............................................. 40
9. DEMOBOARD FILES:...................................................................................................................... 41