Taking the Hard Line

　　Taking the Hard Line

　　作為一個(gè)“海的大門”，FPGAs提供了一個(gè)幾乎無限的平臺(tái)，任何數(shù)字功能，可以實(shí)現(xiàn)使用邏輯表達(dá)式實(shí)現(xiàn)通過查找表的各種寬度。自成立以來，這提供了一個(gè)前所未有的靈活性，而其均勻陣列結(jié)構(gòu)提出了他們的最新的工藝節(jié)點(diǎn)的早期采用者。

　　盡管不斷地在半導(dǎo)體技術(shù)的領(lǐng)先優(yōu)勢，性能仍然是一個(gè)限制因素，在一個(gè)架構(gòu)，依賴于日益復(fù)雜的路由模式和時(shí)鐘結(jié)構(gòu)；正是因?yàn)檫@一原因，廠商第一次實(shí)現(xiàn)關(guān)鍵功能使用硬連接塊的知識產(chǎn)權(quán)（IP）。

　　不竭的需求，更高的性能和最佳的功耗，推動(dòng)FPGA供應(yīng)商整合越來越多的固定功能IP到他們的產(chǎn)品。而中堅(jiān)可以看到這是FPGA技術(shù)的核心利益的侵蝕，事實(shí)上它提供的功能互補(bǔ)，將難以或無法實(shí)現(xiàn)的邏輯結(jié)構(gòu)。

　　One of the core markets for high-end FPGAs has always been telecommunications; here， performance is key and cost can be secondary. To meet this demand， FPGAs now integrate a large amount of IP targeting the data path， such as high-speed Ethernet， as well as other serial transceivers and， most recently， optical interfaces. These sit beside other performance-critical functions such as PLLs and DSP blocks. The ability to add a soft-core processor to handle control path functions means large FPGAs are still very popular in this field， often being preferred over ASICs.

　　While soft cores can tackle many tasks， particularly in the latest and fastest FPGAs， they remain limited and may not be suitable for other tasks where performance is important. Consequently and somewhat naturally， the extension of IP integration saw the introduction of ‘hard’ processor cores; a concept that has taken several iterations to fully realize but is now making a significant impact in many application areas.