1.65GHz的時(shí)鐘輸出分頻器和延遲Fanout Buffer調(diào)整ad9508數(shù)據(jù)表

　　The AD9508 provides clock fanout capability in a design that emphasizes low jitter to maximize system performance. This device benefits applications like clocking data converters with demanding phase noise and low jitter requirements. There are four independent differential clock outputs， each with various types of logic levels available. Available logic types include LVDS （1.65 GHz）， HSTL （1.65 GHz）， and 1.8 V CMOS （250 MHz）。 In 1.8 V CMOS output mode， the differential output becomes two CMOS single-ended signals. The CMOS outputs are 1.8 V logic levels， regardless of the operating supply voltage. Each output has a programmable divider that can be bypassed or be set to divide by any integer up to 1024. In addition， the AD9508 supports a coarse output phase adjustment between the outputs. The device can also be pin programmed for various fixed configurations at power-up without the need for SPI or I2 C programming. The AD9508 is available in a 24-lead LFCSP and operates from a either a single 2.5 V or 3.3 V supply. The temperature range is ?40°C to +85°C.