IS61NLP25672,18mb管道無等待狀態(tài)總線SRAM

　　The 18 Meg ‘NLP/NVP’ product family feature high-speed， low-power synchronous static RAMs designed to provide a burstable， high-performance， ‘no wait’ state， device for networking and communications applications. They are organized as 256K words by 72 bits， 512K words by 36 bits and 1M words by 18 bits， fabricated with ISSI‘s advanced CMOS technology. Incorporating a ’no wait‘ state feature， wait cycles are eliminated when the bus switches from read to write， or write to read. This device integrates a 2-bit burst counter， high-speed SRAM core， and high-drive capability outputs into a single monolithic circuit. Allsynchronousinputspassthroughregistersarecontrolled by a positive-edge-triggered single clock input.Operations may be suspended and all synchronous inputs ignored when Clock Enable， CKE is HIGH.In this state the internal device will hold their previous values. AllRead，WriteandDeselect cyclesareinitiatedby theADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin （MODE） defines the order of the burst sequence.WhentiedHIGH，theinterleavedburst sequence is selected. When tied LOW， the linear burst sequence is selected.