PCI Express Gen2和3代的時(shí)鐘發(fā)生器和風(fēng)扇了eproclock?緩存技術(shù)SL28PCIe14

　　Frequency/Spread Select Pin SS［1:0］ Apply the appropriate logic levels to SS ［1:0］ inputs before CKPWRGD assertion to achieve clock frequency selection. When the clock chip sampled HIGH on CKPWRGD and indicates that the voltage is stable then SS ［1:0］ input values are sampled. This process employs a one-shot functionality and once the CKPWRGD sampled a valid HIGH， all other SS［1:0］， and CKPWRGD transitions are ignored. Serial Data Interface To enhance the flexibility and function of the clock synthesizer， a two-signal serial interface is provided. Through the Serial Data Interface， various device functions， such as individual clock output buffers are individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register changes are normally made at system initialization， if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write， byte read， block write， and block read operations from the controller. For block write/read operation， access the bytes in sequential order from lowest to highest （most significant bit first） with the ability to stop after any complete byte is transferred. For byte write and byte read operations， the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines byte write and byte read protocol. The slave receiver address is 11010010 （D2h）.