基于PWM的CMOS誤差放大器的設(shè)計(jì)

為解決PWM控制器中輸出電壓與基準(zhǔn)電壓的誤差放大問(wèn)題，設(shè)計(jì)了一款高增益、寬帶寬、靜態(tài)電流小的新型誤差放大器，通過(guò)在二級(jí)放大器中間增加一級(jí)緩沖電路，克服補(bǔ)償電容的前饋效應(yīng)，同時(shí)消除補(bǔ)償電容引入的零點(diǎn)。在Cadence軟件平臺(tái)上，經(jīng)過(guò)交流和瞬態(tài)仿真，電路0 dB帶寬達(dá)到55.5 MHz，電壓開環(huán)增益約67.2 dB，相位裕度為83.0°上升建立時(shí)間和下降建立時(shí)間分別為6.7 V/?滋s和5.7 V/?滋s共模抑制比為49.17 dB，電源抑制比為71.39 dB。該誤差放大器已經(jīng)應(yīng)用到了PWM芯片中，使得PWM最大、最小占空比可調(diào)，大幅提升了芯片系統(tǒng)的整體性能。

Abstract:

?In order to solve the error amplify between output voltage and reference voltage in PWM controller. This paper presents a new type of error amplifier， which has a good performance of high gain， high bandwidth and low quiescent current. By increasing a buffer circuit in the middle of the secondary amplifier，the error amplifier could overcome the feed-forward effect of compensation capacitor while eliminating the zero spot lead by the compensation capacitor. In the Cadence software platform， through AC and transient simulation， the test result indicates that the circuit 0dB bandwidth is 55.5MHz， open-loop voltage gain is 67.2dB， phase margin is 83.0°，and rise and fall time of the establishment separately are 6.7V/μs and 5.7V/?滋s，CMRR is 49.17dB， PSRR is71.39dB， The maximum and minimum duty circle of the output of the PWM circuit could be controlled with the help of this type of error amplifier， which increases the performance of the whole system

?

?

?