針對PLL體系結(jié)構(gòu)的頻率合成及規(guī)劃,Frequency Sy

針對PLL體系結(jié)構(gòu)的頻率合成及規(guī)劃:In many applications, it is desired to generate a set of frequencies from a single source frequency. This source could be a temperature controlled crystal oscillator (TCXO), a clock recovered from data, a recovered signal from GPS, or anything else that generates a fixed frequency. The set of frequencies
generated could be several simultaneous fixed
frequencies or a single frequency that is tunable. There may
also be intermediate frequencies that need to be chosen,
such as for the VCO (Voltage Controlled Oscillator) or the
phase detector (PD). Frequency planning is the selection of
these frequencies in an optimal way.
One common situation in frequency planning is when there is
a need to create many fixed frequencies from a single VCO
frequency. In this situation, all frequencies must divide into
the VCO frequency. For example, one could create 12.288
MHz and 30.72 MHz outputs from a single VCO frequency of 61.44 MHz as shown in Figure 1, by dividing the 61.44 MHz VCO frequency by 5 and 2 respectively.