利用DP-FPGA與精電蓬遠(yuǎn)液晶MDLS16265B測(cè)試通過

a8序：利用DP-FPGA與精電蓬遠(yuǎn)液晶MDLS16265B測(cè)試通過

library IEEE;????? ----利用DP-FPGA與精電蓬遠(yuǎn)液晶MDLS16265B測(cè)試?
use IEEE.STD_LOGIC_1164.ALL;??? --顯示magic!
use IEEE.STD_LOGIC_ARITH.ALL;????? --與上面程序功能相同，但顯示速度很快，基本看不清光標(biāo)的閃爍移位
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd_display is
??? generic(N:integer:=25000;
??????????? delay:integer:=1);???? --改了此延時(shí)，造成該情況發(fā)生！

Port ( clk : in std_logic;????
?????? reset:in std_logic;????? --定義一個(gè)拔盤
?????? lcdda : out std_logic;??
?????? lcdrw : out std_logic;??
?????? lcden : out std_logic;??
?????? test :? out? std_logic_vector(7 downto 0)?
?? );???
end lcd_display;
architecture Behavioral of lcd_display is
type state is (set_dlnf,clear_lcd,set_cursor,set_dcb,set_location,write_data);
signal current_state:state;
type rom is array(0 to 5) of std_logic_vector(7 downto 0);
constant datarom:rom:=(("01001101"),("01000001"),("01000111"),("01001001"),("01000011"),("00100001"));
signal clkk:std_logic;
signal data : std_logic_vector(7 downto 0);