STM32硬件設(shè)計手冊

　　On packages with 64 pins or less The VREF+ and VREF- pins are not available， they are internally connected to the ADC voltage supply （VDDA） and ground （VSSA）。 1.1.2 Battery backup To retain the content of the Backup registers when VDD is turned off， the VBAT pin can be connected to an optional standby voltage supplied by a battery or another source. The VBAT pin also powers the RTC unit， allowing the RTC to operate even when the main digital supply （VDD） is turned off. The switch to the VBAT supply is controlled by the power down reset （PDR） circuitry embedded in the Reset block. If no external battery is used in the application， VBAT must be connected externally to VDD. 1.1.3 Voltage regulator The voltage regulator is always enabled after reset. It works in three different modes depending on the application modes. ● in Run mode， the regulator supplies full power to the 1.8 V domain （core， memories and digital peripherals） ● in Stop mode， the regulator supplies low power to the 1.8 V domain， preserving the contents of the registers and SRAM ● in Standby mode， the regulator is powered off. The contents of the registers and SRAM are lost except for those concerned with the Standby circuitry and the Backup domain. 1.2 Power supply schemes The circuit is powered by a stabilized power supply， VDD. ● Caution： – If the ADC is used， the VDD range is limited to 2.4 V to 3.6 V – If the ADC is not used， the VDD range is 2.0 V to 3.6 V ● The VDD pins must be connected to VDD with external stabilization capacitors （eleven 100 nF ceramic capacitor + one Tantalum capacitor （min. 4.7 μF typ.10 μF）。 ● The VBAT pin must be connected to the external battery （1.8 V 《 VBAT 《 3.6 V）。 if no external battery is used， this pin must be connected to VDD with a 100 nF external ceramic stabilization capacitor. ● The VDDA pin must be connected to two external stabilization capacitors （10 nF ceramic + 1 μF Tantalum）。 ● The VREF+ pin can be connected to the VDDA external power supply. If a separate， external reference voltage is applied on VREF+， two 10 nF and 1 μF capacitors must be connected on this pin. In all cases， VREF+ must be kept between 2.4 V and VDDA.