compactpci specification

This Release Note records some issues raised in the course of developing and balloting
PICMG 2.0 Revision 3.0, the CompactPCI core specification.
1. System Management Bus pin assignments. This specification reserves pins on
J1/P1 of all slots and J2/P2 of the System Slot for definition as I2C System
Management Busses by PICMG 2.9, CompactPCI System Management
Specification. These signals have been tentatively assigned by the PICMG 2.9 as
indicated in Section 3.2.7.7 and in Tables 13 through 16 with their notes. The
IPMB_SDA pin is an I2C data bus connecting all slots in a backplane. The
IPMB_SCL pin is the clock associated with that data line, and the IPMB_PWR pin is
a power pin for the IPMB node.
The data and clock pins providing System Slot access to platform devices from J2/P2
were designated ICMB_SDA and ICMB_SCL in the draft specification reviewed and
adopted by the Executive Membership on October 1, 1999. These signal names are
misleading, implying the use of an RS-485 UART bus as specified in the Intel IPMI
documents. These signals are designated SMB_SDA and SMB_SCL in the released
document.
A second System Management power pin, designated ICMB_PWR in the executive
draft, was also reserved on J2/P2 of the System Slot. As of the approval of PICMG
2.0 Revision 3.0, the PICMG 2.9 subcommittee is in doubt as to whether this pin will
actually be used for power, and is considering assigning a different function to this
reserved pin. The released specification accord designates this pin as SMB_RSV.
2. System Slot Hot Swap Signals. This specification designates Pin J1/P1 D15 as a
short BD_SEL# (Board Select) signal in agreement with PICMG 2.1, CompactPCI
Hot Swap Specification, but only on peripheral slots. The pin is shown as a ground
on System Slots. Implementers of CompactPCI boards and systems should anticipate
that this signal may also be designated as BD_SEL# on System Slots in PICMG 2.13,
CompactPCI Redundant System Slot Specification.
J1/P1 Pin B4 is designated as the HEALTHY# signal on System and Peripheral Slots
in this specification