采用準(zhǔn)同步方式實(shí)現(xiàn)基于HDLC的主機(jī)

　　The Teridian 73M2901CE supports the use of a host-based software module for V.42 / MNP 2-4 Error correction Protocol and SDLC operation. These protocol operations require a special mode from the 73M2901CE called quasi-synchronous. This mode of operation is enabled via the ATY4 command. Quasi-synchronous operation （sometimes called the pseudo-synchronous） is a feature of the 73M2901CE modem to perform an asynchronous to synchronous conversion （and vice versa） to the data going over the DTE interface to and from the Host system. The following discussion describes the operation of this mode. HDLC， SDLC， as well as V.42 and MNP Error control protocols， use a synchronous data format. The data is sent via 8 bit octets synchronized by the Transmit and Receive Clocks. A problem arises when sending data to and from the host system because most hosts do not have a synchronous connection to the modem data pump. These systems generally only have an asynchronous UART for sending and receiving serial data. A UART does not use the Transmit and Receive Clocks from the modem; instead it transfers data as characters using extra bits called Start and Stop bits to convey timing information. If the UART is not sending data， the Transmit pin is held in a high， or in a “Marking” state. If the UART wishes to transmit a byte （Octet） of data， a “Start Bit” is transmitted first. A Start Bit or low state is sent for one bit time before the first bit of data is transmitted. After the 8 bits of data are transmitted， the UART returns to the high， or “Marking” state for an additional bit time before more data can be transmitted. This trailing “Marking” time is called the “Stop Bit”。 These extra bits added to the data stream represent 20% more data than what would normally be transmitted with the data bits only. Synchronous data， without a protocol， does not add overhead to the actual data.