HMC849ALP4CE是一款高隔離非反射DC至6 GHz GaAs pHEMT SPDT開關(guān)，采用低成本無引腳表貼封裝。 該開關(guān)非常適合蜂窩/WiMAX/4G基礎(chǔ)設(shè)施應(yīng)用，實現(xiàn)高達60 dB的隔離、0.8 dB的低插入損耗和+52 dBm的輸入IP3。 在最高5 - 6 GHz WiMAX頻段內(nèi)，該器件具有很高的功率處理能力，另外提供+31 dBm的P1dB壓縮點性能。 片內(nèi)電路可在極低直流電流下實現(xiàn)0/+3V或0/+5V單正電壓控制。 使能輸入(EN)設(shè)為邏輯高電平可將該開關(guān)置于“全關(guān)”狀態(tài)。
HMC849ALP4CE 應(yīng)用
- 蜂窩/4G基礎(chǔ)設(shè)施
- WiMAX、WiBro與固定無線
- 汽車遠程信息系統(tǒng)
- 移動無線電
- 測試設(shè)備
The AD9737A/AD9739A are 11-bit and 14-bit, 2.5 GSPS high performance RF DACs that are capable of synthesizing wideband signals from dc up to 3 GHz. The AD9737A/AD9739A are pin and functionally compatible with the AD9739 with the exception that the AD9737A/AD9739A do not support synchronization or RZ mode, and are specified to operate between 1.6 GSPS and 2.5 GSPS.
By elimination of the synchronization circuitry, some nonideal artifacts such as images and discrete clock spurs remain stationary on the AD9737A/AD9739A between power-up cycles, thus allowing for possible system calibration. AC linearity and noise performance remain the same between the AD9739 and the AD9737A/AD9739A.
The inclusion of on-chip controllers simplifies system integration. A dual-port, source synchronous, LVDS interface simplifies the digital interface with existing FGPA/ASIC technology. On-chip controllers are used to manage external and internal clock domain variations over temperature to ensure reliable data transfer from the host to the DAC core. A serial peripheral interface (SPI) is used for device configuration as well as readback of status registers.
The AD9737A/AD9739A are manufactured on a 0.18 μm CMOS process and operate from 1.8 V and 3.3 V supplies. They are supplied in a 160-ball chip scale ball grid array for reduced package parasitics.
AD9739ABBCZ Product Highlights
Ability to synthesize high quality wideband signals with bandwidths of up to 1.25 GHz in the first or second Nyquist zone.
A proprietary quad-switch DAC architecture provides exceptional ac linearity performance while enabling mixmode operation.
A dual-port, double data rate, LVDS interface supports the maximum conversion rate of 2500 MSPS.
On-chip controllers manage external and internal clock domain skews.
Programmable differential current output with an 8.66 mA to 31.66 mA range.
AD9739ABBCZ Applications
Broadband communications systems
DOCSIS CMTS systems
Military jammers
Instrumentation, automatic test equipment
Radar, avionics
