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      TMS320C6743 定點(diǎn)/浮點(diǎn)數(shù)字信號處理器

      數(shù)據(jù)：

      描述

      C6743器件是一款基于C674x DSP內(nèi)核的低功耗數(shù)字信號處理器。與TMS320C6000™DSP平臺(tái)的其他成員相比，該器件的功耗顯著降低。

      C6743器件使原始設(shè)備制造商（OEM）和原始設(shè)計(jì)制造商（ODM）能夠快速推向市場高處理性能。

      C6743 DSP內(nèi)核采用基于緩存的兩級架構(gòu)。 1級程序高速緩存（L1P）是32 KB直接映射高速緩存，1級數(shù)據(jù)高速緩存（L1D）是32 KB雙向組關(guān)聯(lián)高速緩存。 Level 2程序緩存（L2P）由128 KB的內(nèi)存空間組成，在程序和數(shù)據(jù)空間之間共享。 L2內(nèi)存可以配置為映射內(nèi)存，緩存或兩者的組合。

      外設(shè)集包括：帶管理數(shù)據(jù)輸入/輸出（MDIO）模塊的10/100 Mbps以太網(wǎng)MAC（EMAC）;兩個(gè)I 2 C總線接口;兩個(gè)帶有14/9串行器和FIFO緩沖器的多通道音頻串行端口（McASP）;兩個(gè)64位通用定時(shí)器，每個(gè)都可配置（一個(gè)可配置為看門狗）;多達(dá)8個(gè)16引腳的通用輸入/輸出（GPIO），具有可編程中斷/事件生成模式，與其他外設(shè)復(fù)用;兩個(gè)UART接口（一個(gè)具有 RTS 和 CTS ）;三個(gè)增強(qiáng)型高分辨率脈沖寬度調(diào)制器（eHRPWM）外設(shè);三個(gè)32位增強(qiáng)型捕獲（eCAP）模塊外設(shè)，可配置為3個(gè)捕獲輸入或3個(gè)輔助脈沖寬度調(diào)制器（APWM）輸出;兩個(gè)32位增強(qiáng)型正交編碼脈沖（eQEP）外設(shè);和2個(gè)外部存儲(chǔ)器接口（EMIF）：用于較慢存儲(chǔ)器或外設(shè)的異步外部存儲(chǔ)器接口（EMIFA），以及用于SDRAM的高速存儲(chǔ)器接口（EMIFB）。

      以太網(wǎng)媒體訪問控制器（EMAC）提供C6743和網(wǎng)絡(luò)之間的有效接口。 EMAC支持10Base-T和100Base-TX，或半雙工或全雙工模式下的10 Mbps和100 Mbps。此外，MDIO接口可用于PHY配置。

      豐富的外設(shè)集可以控制外部外圍設(shè)備并與外部處理器通信。有關(guān)每個(gè)外圍設(shè)備的詳細(xì)信息，請參閱本文檔后面的相關(guān)章節(jié)以及相關(guān)的外圍設(shè)備參考指南。

      特性

      • Applications
        • Networking
        • High-Speed Encoding
        • Professional Audio™
      • Software Support
        • TI DSP/BIOS™
        • Chip Support Library and DSP Library
      • 375-MHz TMS320C674x Fixed- and Floating-Point VLIW DSP Core
        • Load-Store Architecture with Nonaligned Support
        • 64 General-Purpose Registers (32-Bit)
        • Six ALU (32- and 40-Bit) Functional Units
          • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
          • Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
          • Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
        • Two Multiply Functional Units
          • Mixed-Precision IEEE Floating Point Multiply Supported up to:
            • 2 SP x SP -> SP Per Clock
            • 2 SP x SP -> DP Every Two Clocks
            • 2 SP x DP -> DP Every Three Clocks
            • 2 DP x DP -> DP Every Four Clocks
          • Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
        • Instruction Packing Reduces Code Size
        • All Instructions Conditional
        • Hardware Support for Modulo Loop
          Operation
        • Protected Mode Operation
        • Exceptions Support for Error Detection and Program Redirection
      • C674x Instruction Set Features
        • Superset of the C67x+ and C64x+ ISAs
        • 3000 MIPS and 2250 MFLOPS C674x
        • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
        • 8-Bit Overflow Protection
        • Bit-Field Extract, Set, Clear
        • Normalization, Saturation, Bit-Counting
        • Compact 16-Bit Instructions
      • C674x Two-Level Cache Memory Architecture
        • 32KB of L1P Program RAM/Cache
        • 32KB of L1D Data RAM/Cache
        • 128KB of L2 Unified Mapped RAM/Cache
        • Flexible RAM/Cache Partition (L1 and L2)
      • Enhanced Direct Memory Access Controller 3 (EDMA3):
        • 2 Transfer Controllers
        • 32 Independent DMA Channels
        • 8 Quick DMA Channels
        • Programmable Transfer Burst Size
      • 3.3-V LVCMOS I/Os
      • Two External Memory Interfaces:
        • EMIFA
          • NOR (8-Bit-Wide Data)
          • NAND (8-Bit-Wide Data)
        • EMIFB
          • 16-bit SDRAM, up to 128MB
      • Two Configurable 16550-Type UART Modules:
        • UART0 with Modem Control Signals
        • 16-Byte FIFO
        • 16x or 13x Oversampling Option
      • One Serial Peripheral Interface (SPI) with One Chip Select
      • Multimedia Card (MMC)/Secure Digital (SD)
      • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
      • Programmable Real-Time Unit Subsystem (PRUSS)
        • Two Independent Programmable Real-Time Unit (PRU) Cores
          • 32-Bit Load-Store RISC Architecture
          • 4KB of Instruction RAM per Core
          • 512 Bytes of Data RAM per Core
          • PRUSS can be Disabled Through Software to Save Power
          • Register 30 of each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores
        • Standard Power-Management Mechanism
          • Clock Gating
          • Entire Subsystem Under a Single PSC Clock Gating Domain
        • Dedicated Interrupt Controller
        • Dedicated Switched Central Resource
      • Two Multichannel Audio Serial Ports (McASPs):
        • Supports TDM, I2S, and Similar Formats
        • FIFO Buffers for Transmit and Receive
      • 10/100 Mbps RMII Ethernet Media Access Controller (EMAC):
        • IEEE 802.3 Compliant (3.3-V I/O Only)
        • RMII Media-Independent Interface
        • Management Data I/O (MDIO) Module
      • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
      • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit Timers)
      • Three Enhanced Pulse Width Modulators (eHRPWMs):
        • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
        • 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
        • Dead-Band Generation
        • PWM Chopping by High-Frequency Carrier
        • Trip Zone Input
      • Three 32-Bit Event Capture (eCAP) Modules:
        • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
        • Single-Shot Capture of up to Four Event Time-Stamps
      • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
      • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
      • 176-Pin Thin Quad Flat Pack (TQFP) [PTP Suffix], 0.5-mm Pin Pitch
      • Commercial or Automotive Temperature

      參數(shù) 與其它產(chǎn)品相比 音頻處理器

       
      DSP
      DSP MHz (Max)
      Arm CPU
      Operating Systems
      DRAM
      On-Chip L2 Cache/RAM
      Approx. Price (US$)
      Operating Temperature Range (C)
      McASP
      McBSP
      USB
      EMAC
      Package Group
      PCI/PCIe
      I2C
      UART (SCI)
      DSP MMACS
      Other Hardware Acceleration
      TMS320C6743
      1 C674x    
      200
      375    
      N/A    
      TI RTOS    
      SDRAM    
      128 KB    
      8.55 | 1ku    
      -40 to 125
      0 to 90    
      2    
      0    
      0    
      10/100    
      BGA
      HLQFP    
      N/A    
      2    
      2    
      3000    
      PRU-ICSS    

      方框圖 (1)


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