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      OMAP-L137 C6000 DSP+ARM 處理器

      數(shù)據(jù)：

      描述

      OMAP-L137器件是一款基于ARM926EJ-S和TMS320C674x DSP內(nèi)核的低功耗應(yīng)用處理器。它的功耗顯著低于DSP的TMS320C6000平臺的其他成員。

      OMAP-L137器件使原始設(shè)備制造商（OEM）和原始設(shè)計(jì)制造商（ODM）能夠快速推向市場通過完全集成的混合處理器解決方案的最大靈活性，提供強(qiáng)大的操作系統(tǒng)支持，豐富的用戶界面和高處理性能。

      OMAP-L137器件的雙核架構(gòu)提供了DSP和DSP的優(yōu)勢。精簡指令集計(jì)算機(jī)（RISC）技術(shù)，集成了高性能TMS320C674x DSP內(nèi)核和ARM926EJ-S內(nèi)核。

      ARM926EJ-S是一個(gè)32位RISC處理器內(nèi)核，可執(zhí)行32位或16位位指令和處理32位，16位或8位數(shù)據(jù)。核心使用流水線操作，以便處理器和內(nèi)存系統(tǒng)的所有部分可以連續(xù)運(yùn)行。

      ARM內(nèi)核具有協(xié)處理器15（CP15），保護(hù)模塊以及數(shù)據(jù)和程序內(nèi)存管理單元（MMU）表后備緩沖區(qū)。 ARM內(nèi)核具有單獨(dú)的16 KB指令和16 KB的數(shù)據(jù)高速緩存。兩個(gè)內(nèi)存塊都與虛擬索引虛擬標(biāo)記（VIVT）進(jìn)行四向關(guān)聯(lián)。 ARM內(nèi)核還具有8KB的RAM（向量表）和64KB的ROM。

      OMAP-L137 DSP內(nèi)核使用基于高速緩存的兩級架構(gòu)。 1級程序高速緩存（L1P）是32 KB直接映射高速緩存，1級數(shù)據(jù)高速緩存（L1D）是32 KB雙向組關(guān)聯(lián)高速緩存。 2級程序高速緩存（L2P）由256 KB內(nèi)存空間組成，在程序和數(shù)據(jù)空間之間共享。 L2內(nèi)存可以配置為映射內(nèi)存，緩存或兩者的組合。盡管ARM L2和系統(tǒng)中的其他主機(jī)可以訪問DSP L2，但是其他主機(jī)可以使用額外的128KB RAM共享內(nèi)存，而不會影響DSP性能。

      外設(shè)集包括：帶管理數(shù)據(jù)輸入/輸出（MDIO）模塊的10/100 Mbps以太網(wǎng)MAC（EMAC）;兩個(gè)I 2 C總線接口; 3個(gè)多聲道音頻串行端口（McASP），帶有16/12/4串行器和FIFO緩沖器;兩個(gè)64位通用定時(shí)器，每個(gè)都可配置（一個(gè)可配置為看門狗）;可配置的16位主機(jī)端口接口（HPI）;多達(dá)8個(gè)16引腳的通用輸入/輸出（GPIO），具有可編程中斷/事件生成模式，與其他外設(shè)復(fù)用; 3個(gè)UART接口（一個(gè)具有 RTS 和 CTS ）;三個(gè)增強(qiáng)型高分辨率脈沖寬度調(diào)制器（eHRPWM）外設(shè);三個(gè)32位增強(qiáng)型捕獲（eCAP）模塊外設(shè)，可配置為3個(gè)捕獲輸入或3個(gè)輔助脈沖寬度調(diào)制器（APWM）輸出;兩個(gè)32位增強(qiáng)型正交編碼脈沖（eQEP）外設(shè);和2個(gè)外部存儲器接口：用于較慢存儲器或外設(shè)的異步和SDRAM外部存儲器接口（EMIFA），以及用于SDRAM的高速存儲器接口（EMIFB）。

      以太網(wǎng)媒體訪問控制器（EMAC）提供OMAP-L137設(shè)備與網(wǎng)絡(luò)之間的高效接口。 EMAC支持10Base-T和100Base-TX，或半雙工或全雙工模式下的10 Mbps和100 Mbps。此外，MDIO接口可用于PHY配置。

      HPI，I2C，SPI，USB1.1和USB2.0端口允許OMAP-L137設(shè)備輕松控制外圍設(shè)備和/或與主機(jī)處理器通信。

      豐富的外設(shè)集提供了控制外部外圍設(shè)備和與外部處理器通信的能力。有關(guān)每個(gè)外設(shè)的詳細(xì)信息，請參閱本文檔后面的相關(guān)章節(jié)以及相關(guān)的外設(shè)參考指南。

      OMAP-L137器件具有一整套用于ARM和DSP的開發(fā)工具。這些包括C編譯器，用于簡化編程和調(diào)度的DSP匯編優(yōu)化器，以及用于查看源代碼執(zhí)行的Windows®調(diào)試器接口。

      特性

      • Software Support
        • TI DSP/BIOS
        • Chip Support Library and DSP Library
      • Dual Core SoC
        • 375- and 456-MHz ARM926EJ-S RISC MPU
        • 375- and 456-MHz C674x VLIW DSP
      • ARM926EJ-S Core
        • 32-Bit and 16-Bit (Thumb®) Instructions
        • DSP Instruction Extensions
        • Single Cycle MAC
        • ARM® Jazelle® Technology
        • Embedded ICE-RT™ for Real-Time Debug
      • ARM9™ Memory Architecture
        • 16KB of Instruction Cache
        • 16KB of Data Cache
        • 8KB of RAM (Vector Table)
        • 64KB of ROM
      • C674x Instruction Set Features
        • Superset of the C67x+ and C64x+ ISAs
        • Up to 3648 MIPS and 2736 MFLOPS C674x
        • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
        • 8-Bit Overflow Protection
        • Bit-Field Extract, Set, Clear
        • Normalization, Saturation, Bit-Counting
        • Compact 16-Bit Instructions
      • C674x Two-Level Cache Memory Architecture
        • 32KB of L1P Program RAM/Cache
        • 32KB of L1D Data RAM/Cache
        • 256KB of L2 Unified Mapped RAM/Cache
        • Flexible RAM/Cache Partition (L1 and L2)
      • Enhanced Direct Memory Access Controller 3 (EDMA3):
        • 2 Transfer Controllers
        • 32 Independent DMA Channels
        • 8 Quick DMA Channels
        • Programmable Transfer Burst Size
      • TMS320C674x Fixed- and Floating-Point VLIW DSP Core
        • Load-Store Architecture with Nonaligned Support
        • 64 General-Purpose Registers (32-Bit)
        • Six ALU (32- and 40-Bit) Functional Units
          • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
          • Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
          • Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
        • Two Multiply Functional Units
          • Mixed-Precision IEEE Floating Point Multiply Supported up to:
            • 2 SP x SP -> SP Per Clock
            • 2 SP x SP -> DP Every Two Clocks
            • 2 SP x DP -> DP Every Three Clocks
            • 2 DP x DP -> DP Every Four Clocks
          • Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
        • Instruction Packing Reduces Code Size
        • All Instructions Conditional
        • Hardware Support for Modulo Loop
          Operation
        • Protected Mode Operation
        • Exceptions Support for Error Detection and Program Redirection
      • 128KB of RAM Shared Memory
      • 3.3-V LVCMOS I/Os (Except for USB Interfaces)
      • Two External Memory Interfaces:
        • EMIFA
          • NOR (8- or 16-Bit-Wide Data)
          • NAND (8- or 16-Bit-Wide Data)
          • 16-Bit SDRAM with 128-MB Address Space
        • EMIFB
          • 32-Bit or 16-Bit SDRAM with 256-MB Address Space
      • Three Configurable 16550-Type UART Modules:
        • UART0 with Modem Control Signals
        • Autoflow Control Signals (CTS, RTS) on UART0 Only
        • 16-Byte FIFO
        • 16x or 13x Oversampling Option
      • LCD Controller
      • Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
      • Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
      • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
      • One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth
      • Programmable Real-Time Unit Subsystem (PRUSS)
        • Two Independent Programmable Realtime Unit (PRU) Cores
          • 32-Bit Load and Store RISC Architecture
          • 4KB of Instruction RAM per Core
          • 512 Bytes of Data RAM per Core
          • PRUSS can be Disabled via Software to Save Power
        • Standard Power-Management Mechanism
          • Clock Gating
          • Entire Subsystem Under a Single PSC Clock Gating Domain
        • Dedicated Interrupt Controller
        • Dedicated Switched Central Resource
      • USB 1.1 OHCI (Host) with Integrated PHY (USB1)
      • USB 2.0 OTG Port with Integrated PHY (USB0)
        • USB 2.0 High- and Full-Speed Client
        • USB 2.0 High-, Full-, and Low-Speed Host
        • End Point 0 (Control)
        • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
      • Three Multichannel Audio Serial Ports (McASPs):
        • Six Clock Zones and 28 Serial Data Pins
        • Supports TDM, I2S, and Similar Formats
        • DIT-Capable (McASP2)
        • FIFO Buffers for Transmit and Receive
      • 10/100 Mbps Ethernet MAC (EMAC):
        • IEEE 802.3 Compliant (3.3-V I/O Only)
        • RMII Media-Independent Interface
        • Management Data I/O (MDIO) Module
      • Real-Time Clock with 32-kHz Oscillator and Separate Power Rail
      • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
      • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
      • Three Enhanced Pulse Width Modulators (eHRPWMs):
        • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
        • 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
        • Dead-Band Generation
        • PWM Chopping by High-Frequency Carrier
        • Trip Zone Input
      • Three 32-Bit Enhanced Capture (eCAP) Modules:
        • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
        • Single-Shot Capture of up to Four Event Time-Stamps
      • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
      • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
      • Commercial, Industrial, Extended, or Automotive Temperature

      參數(shù) 與其它產(chǎn)品相比 音頻處理器

       
      DSP
      DSP MHz (Max)
      Arm CPU
      Arm MHz (Max.)
      Operating Systems
      DRAM
      On-Chip L2 Cache/RAM
      Approx. Price (US$)
      McASP
      McBSP
      USB
      EMAC
      Package Group
      PCI/PCIe
      I2C
      UART (SCI)
      DSP MMACS
      Other Hardware Acceleration
      OMAP-L137
      1 C674x    
      456    
      1 ARM9    
      456    
      Linux
      TI RTOS    
      SDRAM    
      256 KB (DSP)    
      14.30 | 1ku    
      3    
      0    
      2    
      10/100    
      BGA    
      N/A    
      2    
      3    
      3648    
      PRU-ICSS    

      技術(shù)文檔

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