時(shí)鐘代碼 - 異步FIFO的設(shè)計(jì)分析及詳細(xì)代碼

4、sync_w2r.v 將 wclk 時(shí)鐘域的格雷碼形式的寫(xiě)指針同步到 rclk 時(shí)鐘域

module sync_w2r
#(parameter ADDRSIZE = 4)
(
output reg [ADDRSIZE:0] rq2_wptr, //寫(xiě)指針同步到讀時(shí)鐘域
input [ADDRSIZE:0] wptr, //格雷碼形式的寫(xiě)指針
input rclk, rrst_n
);

reg [ADDRSIZE:0] rq1_wptr;

always @(posedge rclk or negedge rrst_n)
if (!rrst_n)begin
rq1_wptr <= 0;
rq2_wptr <= 0;
end
else begin
rq1_wpt <= wptr;
rq2_wptr <= rq1_wptr;
end

endmodule

5、rptr_empty.v 將 sync_w2r.v 同步后的寫(xiě)指針與 rclk 時(shí)鐘域的讀指針進(jìn)行比較生成都空信號(hào)

module rptr_empty
#(
parameter ADDRSIZE = 4
)
(
output reg rempty,
output [ADDRSIZE-1:0] raddr, //二進(jìn)制形式的讀指針
output reg [ADDRSIZE :0] rptr, //格雷碼形式的讀指針
input [ADDRSIZE :0] rq2_wptr, //同步后的寫(xiě)指針
input rinc, rclk, rrst_n
);
reg [ADDRSIZE:0] rbin;
wire [ADDRSIZE:0] rgraynext, rbinnext;
// GRAYSTYLE2 pointer
//將二進(jìn)制的讀指針與格雷碼進(jìn)制的讀指針同步
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) begin
rbin <= 0;
rptr <= 0;
end
else begin
rbin<=rbinnext; //直接作為存儲(chǔ)實(shí)體的地址
rptr<=rgraynext;//輸出到 sync_r2w.v模塊，被同步到 wrclk 時(shí)鐘域
end
// Memory read-address pointer (okay to use binary to address memory)
assign raddr = rbin[ADDRSIZE-1:0]; //直接作為存儲(chǔ)實(shí)體的地址，比如連接到RAM存儲(chǔ)實(shí)體的讀地址端。
assign rbinnext = rbin + (rinc & ~rempty); //不空且有讀請(qǐng)求的時(shí)候讀指針加1
assign rgraynext = (rbinnext>>1) ^ rbinnext; //將二進(jìn)制的讀指針轉(zhuǎn)為格雷碼
// FIFO empty when the next rptr == synchronized wptr or on reset
assign rempty_val = (rgraynext == rq2_wptr); //當(dāng)讀指針等于同步后的寫(xiě)指針，則為空。
always @(posedge rclk or negedge rrst_n)
if (!rrst_n)
rempty <= 1'b1;
else
rempty <= rempty_val;

endmodule

6、wptr_full.v 將 sync_r2w.v 同步后的讀指針與wclk 時(shí)鐘域的寫(xiě)指針進(jìn)行比較生成寫(xiě)滿信號(hào)

module wptr_full
#(
parameter ADDRSIZE = 4
)
(
output reg wfull,
output [ADDRSIZE-1:0] waddr,
output reg [ADDRSIZE :0] wptr,
input [ADDRSIZE :0] wq2_rptr,
input winc, wclk, wrst_n
);
reg [ADDRSIZE:0] wbin;
wire [ADDRSIZE:0] wgraynext, wbinnext;
// GRAYSTYLE2 pointer
always @(posedge wclk or negedge wrst_n)
if (!wrst_n)
{wbin, wptr} <= 0;
else
{wbin, wptr} <= {wbinnext, wgraynext};
// Memory write-address pointer (okay to use binary to address memory)
assign waddr = wbin[ADDRSIZE-1:0];
assign wbinnext = wbin + (winc & ~wfull);
assign wgraynext = (wbinnext>>1) ^ wbinnext; //二進(jìn)制轉(zhuǎn)為格雷碼
//-----------------------------------------------------------------
assign wfull_val = (wgraynext=={~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]}); //當(dāng)最高位和次高位不同其余位相同時(shí)則寫(xiě)指針超前于讀指針一圈，即寫(xiě)滿。后面會(huì)詳細(xì)解釋。
always @(posedge wclk or negedge wrst_n)
if (!wrst_n)
wfull <= 1'b0;
else
wfull <= wfull_val;

endmodule

7、測(cè)試文件

`timescale 1ns /1ns

module test();
reg [7:0] wdata;
reg winc, wclk, wrst_n;
reg rinc, rclk, rrst_n;
wire [7:0] rdata;
wire wfull;
wire rempty;

fifo

u_fifo (
.rdata(rdata),
.wfull(wfull),
.rempty(rempty),
.wdata (wdata),
.winc (winc),
.wclk (wclk),
.wrst_n(wrst_n),
.rinc(rinc),
.rclk(rclk),
.rrst_n(rrst_n)
);
localparam CYCLE = 20;
localparam CYCLE1 = 40;

//時(shí)鐘周期，單位為ns，可在此修改時(shí)鐘周期。

//生成本地時(shí)鐘50M
initial begin
wclk = 0;
forever
#(CYCLE/2)
wclk=~wclk;
end
initial begin
rclk = 0;
forever
#(CYCLE1/2)
rclk=~rclk;
end

//產(chǎn)生復(fù)位信號(hào)
initial begin
wrst_n = 1;
#2;
wrst_n = 0;
#(CYCLE*3);
wrst_n = 1;
end

initial begin
rrst_n = 1;
#2;
rrst_n = 0;
#(CYCLE*3);
rrst_n = 1;
end

always @(posedge wclk or negedge wrst_n)begin
if(wrst_n==1'b0)begin
winc <= 0;
rinc <= 0;
end
else begin
winc <= $random;
rinc <= $random;
end
end

always @(posedge rclk or negedge rrst_n)begin
if(rrst_n==1'b0)begin
rinc <= 0;
end
else begin
rinc <= $random;
end
end
always@(*)begin
if(winc == 1)
wdata= $random ;
else
wdata = 0;
end
endmodule

8、仿真結(jié)果

由于截圖篇幅的限制請(qǐng)自己驗(yàn)證仿真。