- FIFO 同步、異步以及Verilog代碼實(shí)現(xiàn)

這個(gè)是基于RAM的異步FIFO代碼，個(gè)人認(rèn)為代碼結(jié)構(gòu)簡(jiǎn)單易懂，非常適合于考試中填寫。記得10月份參加威盛的筆試的時(shí)候，就考過(guò)異步FIFO的實(shí)現(xiàn)。想當(dāng)初要是早點(diǎn)復(fù)習(xí)，可能就可以通過(guò)威盛的筆試了。
與之前的用RAM實(shí)現(xiàn)的同步FIFO的程序相比，異步更為復(fù)雜。增加了讀寫控制信號(hào)的跨時(shí)鐘域的同步。此外，判空與判滿的也稍有不同。
module fifo1(rdata, wfull, rempty, wdata, winc, wclk, wrst_n,rinc, rclk, rrst_n);parameter DSIZE = 8; parameter ASIZE = 4;output [DSIZE-1:0] rdata;output wfull;output rempty;input [DSIZE-1:0] wdata;input winc, wclk, wrst_n;input rinc, rclk, rrst_n;reg wfull,rempty;reg [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr, wq1_rptr,rq1_wptr;reg [ASIZE:0] rbin, wbin;reg [DSIZE-1:0] mem[0:(1<>1) ^ rbinnext;// FIFO empty when the next rptr == synchronized wptr or on resetassign rempty_val = (rgraynext == rq2_wptr);always @(posedge rclk or negedge rrst_n)beginif (!rrst_n) rempty <= 1'b1;else rempty <= rempty_val;end//---------------wfull產(chǎn)生與waddr產(chǎn)生------------------------------always @(posedge wclk or negedge wrst_n) // GRAYSTYLE2 pointerif (!wrst_n) {wbin, wptr} <= 0;else {wbin, wptr} <= {wbinnext, wgraynext};// Memory write-address pointer (okay to use binary to address memory)assign waddr = wbin[ASIZE-1:0];assign wbinnext = wbin + (winc & ~wfull);assign wgraynext = (wbinnext>>1) ^ wbinnext;assign wfull_val = (wgraynext=={~wq2_rptr[ASIZE:ASIZE-1], wq2_rptr[ASIZE-2:0]}); //:ASIZE-1]always @(posedge wclk or negedge wrst_n)if (!wrst_n) wfull <= 1'b0;else wfull <= wfull_val;endmodule
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異步FIFO的Verilog代碼 之二