Xilinx FPGA普通IO作PLL時(shí)鐘輸入

在xilinx ZC7020的片子上做的實(shí)驗(yàn);

[結(jié)論]

普通IO不能直接作PLL的時(shí)鐘輸入,專用時(shí)鐘管腳可以;

普通IO可以通過BUFG再連到PLL的時(shí)鐘輸入上,但要修改PLL的設(shè)置 input clk的選項(xiàng)中要選擇"No Buffer";

具體內(nèi)部布局分配可以通過 Xilinx的FPGA Editor來(lái)查看,

ZYNQ的時(shí)鐘管理也和之前的片子略有不同,之后在另一篇介紹,相關(guān)文檔

[Demo1]
// demo1 two bufg connect

module iobuf(

input clk,

input rst,

output led

);

wire clkin_w;

BUFG BUFG_inst (

.O(clkin_w), // Clock buffer output

.I(clk) // Clock buffer input

);

pll0 u_pll0(

.CLK_IN1(clkin_w), // IN

.CLK_OUT1(clkout), // OUT

.RESET(rst)); // IN

assign led = clkout;

endmodule

鎖相環(huán)PLL默認(rèn)輸入前端有個(gè)BUFG單元,而兩個(gè)BUFG不能相連,所以會(huì)報(bào)這樣的錯(cuò):

ERROR:NgdBuild:770 - IBUFG 'u_pll0/clkin1_buf' and BUFG 'BUFG_inst' on net

'clkin_w' are lined up in series. Buffers of the same direction cannot be

placed in series.

ERROR:NgdBuild:924 - input pad net 'clkin_w' is driving non-buffer primitives:

[Demo2]

// demo2 regular io directly connect to PLL

module iobuf(

input clk,

input rst,

output led

);
wire clkin_w;

/*

BUFG BUFG_inst (

.O(clkin_w), // Clock buffer output

.I(clk) // Clock buffer input

);

*/

pll0 u_pll0(

.CLK_IN1(clk), // IN

.CLK_OUT1(clkout), // OUT

.RESET(rst)); // IN

assign led = clkout;

endmodule

普通IO不能直接做鎖相環(huán)的輸入,所以會(huì)報(bào)這樣的錯(cuò):

ERROR:Place:1397 - A clock IOB / MMCM clock component pair have been found that

are not placed at an optimal clock IOB / MMCM site pair. The clock IOB

component is placed at site . The corresponding MMCM component

is placed at site . The clock IO can

use the fast path between the IOB and the MMCM if the IOB is placed on a

Clock Capable IOB site that has dedicated fast path to MMCM sites within the

same clock region. You may want to analyze why this problem exists and

correct it. If this sub optimal condition is acceptable for this design, you

may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this

message to a WARNING and allow your design to continue. However, the use of

this override is highly discouraged as it may lead to very poor timing

results. It is recommended that this error condition be corrected in the

design. A list of all the COMP.PINs used in this clock placement rule is

ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

如果有ucf中加上這句約束:

NET clk CLOCK_DEDICATED_ROUTE = FALSE;

依舊會(huì)報(bào)錯(cuò),在ZYNQ7000系列,這樣還是通不過,如下:

ERROR:PhysDesignRules:2256 - Unsupported MMCME2_ADV configuration. The signal

u_pll0/clkin1 on the CLKIN1 pin of MMCME2_ADV comp u_pll0/mmcm_adv_inst with

COMPENSATION mode ZHOLD must be driven by a clock capable IOB.

ERROR:Pack:1642 - Errors in physical DRC.

使用普通的IO,再連接bufg來(lái)連到時(shí)鐘線上,

仍會(huì)報(bào)這樣的錯(cuò)誤,因?yàn)檫€是兩bufg相連了:

ERROR:NgdBuild:770 - IBUFG 'u_pll0/clkin1_buf' and BUFG 'BUFG_inst' on net

'clkin_w' are lined up in series. Buffers of the same direction cannot be

placed in series.

ERROR:NgdBuild:924 - input pad net 'clkin_w' is driving non-buffer primitives:

[Demo3]
// dem3 regular io with BUFG then connect to PLL which with"No Buffer" setting

module iobuf(

input clk,

input rst,

output led

);

wire clkin_w;

BUFG BUFG_inst (

.O(clkin_w), // Clock buffer output

.I(clk) // Clock buffer input

);

pll0 u_pll0(

.CLK_IN1(clkin_w), // IN

.CLK_OUT1(clkout), // OUT

.RESET(rst)); // IN

assign led = clkout;

endmodule

PLL的設(shè)置如下圖,

這樣普通IO就可以當(dāng)作PLL的時(shí)鐘輸入了,順利產(chǎn)生bit;

時(shí)鐘還是最好用全局時(shí)鐘IO,畫圖時(shí)一定要注意:)

zc702里沒有g(shù)lobal clock的概念了,但有了很多專用時(shí)鐘腳,用起來(lái)一樣;