SystemVerilog中的tagged Unions是什么

在Systemverilog中,union可以被聲明為tagged unions。

union tagged {
 int a;
 byte b;
 bit [15:0] c;
 } data;

tagged union包含一個(gè)隱式成員，該成員存儲(chǔ)tag，也就是標(biāo)記，它表示這個(gè)union最終存儲(chǔ)的到底是哪一個(gè)成員。

tagged union 是一種類型檢查（type-checked）union.

這意味著你不能寫入union中的一個(gè)成員，而讀取另外一個(gè)成員。因?yàn)樵谶@期間，tagged union會(huì)進(jìn)行讀寫類型檢查

data = tagged a 32'hffff_ffff;

如果從不同的union成員中讀取值，仿真器則會(huì)報(bào)錯(cuò):

module tagged_union_example;
logic [31:0] x;
typedef union tagged {
int a;
byte b;
bit [15:0] c;
} data;

data d1;
initial begin
d1 = tagged a 32'hffff_ffff; //write to 'a'
//read from 'b'. Since 'a' was written last, cannot access
//'b'. - Error
x = d1.b;
$display("x = %h",x);
end
endmodule

在上面的例子中，我們創(chuàng)建了一個(gè)tagged union " data "，并聲明" d1 "為" data "類型。然后我們寫入成員a:

d1 = tagged a 32'hffff_ffff;

然后我們讀取值“d1.b”。因?yàn)樽x寫的成員類型不同，所以會(huì)打印錯(cuò)誤信息：

Error-[TU-INVMEMUSG] Invalid member usage of a tagged union.
testbench.sv, 15
Member of a tagged union referred is not valid since a different member is
in use. The expected tag is 'a', but tag 'b' is used.
Please check which member of the tagged union is in use.
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審核編輯：劉清