數(shù)字硬件建模SystemVerilog

數(shù)字硬件建模SystemVerilog-使用結(jié)構(gòu)體和聯(lián)合體的例子

使用結(jié)構(gòu)體和聯(lián)合體的例子

結(jié)構(gòu)體和聯(lián)合體可以包括壓縮或非壓縮數(shù)組，壓縮結(jié)構(gòu)體或聯(lián)合體只能包括壓縮數(shù)組。

壓縮和非壓縮的數(shù)組可以將結(jié)構(gòu)體和聯(lián)合體作為元素包含在數(shù)組中。在壓縮數(shù)組中，結(jié)構(gòu)體或聯(lián)合體也必須是壓縮的。

數(shù)組可以包含自定義結(jié)構(gòu)體和自定義聯(lián)合體。綜合支持?jǐn)?shù)組中的壓縮或非壓縮結(jié)構(gòu)體。

示例4-8說明了如何使用結(jié)構(gòu)體數(shù)組，該示例是一個(gè)指令寄存器模型，其中包含32條指令的非壓縮數(shù)組，每條指令是一個(gè)復(fù)合值，表示為壓縮結(jié)構(gòu)體。指令中的操作數(shù)可以是有符號(hào)的或無符號(hào)的，表示為兩種類型的聯(lián)合體。

該指令寄存器的輸入包括單獨(dú)的操作數(shù)、一個(gè)操作碼和一個(gè)指示操作數(shù)是有符號(hào)的還是無符號(hào)的標(biāo)志。該模型將這些單獨(dú)的輸入值加載到指令寄存器陣列中。一種寫入指針輸入控件，用于加載數(shù)據(jù)。該模型的輸出是單個(gè)指令結(jié)構(gòu)體，使用讀指針輸入從指令寄存器中選擇。

本例使用了前面示例4-6中所示的相同包項(xiàng)。

示例4-6：包含結(jié)構(gòu)體和聯(lián)合體定義的包

//
//Packagewithunionandstructuredefinitions
//
//`begin_keywords"1800-2012"http://useSystemVerilog-2012keywords
`define_4bit//use4-bitdatafortestingsynthesis
//`define_32bit//use32-bitdatawordsize
//`define_64bit//use64-bitdatawordsize
packagedefinitions_pkg;
`ifdef_4bit
typedeflogic[3:0]uword_t;
typedeflogicsigned[3:0]sword_t;
`elsif_64bit
typedeflogic[63:0]uword_t;
typedeflogicsigned[63:0]sword_t;
`else//defaultis32-bitvectors
typedeflogic[31:0]uword_t;
typedeflogicsigned[31:0]sword_t;
`endif

typedefenumlogic[2:0]{ADD,SUB,MULT,DIV}op_t;
typedefenumlogic{UNSIGNED,SIGNED}operand_type_t;

//Packedunionrepresentsavariablethatcanstore
//differenttypes
typedefunionpacked{
uword_tu_data;
sword_ts_data;
}data_t;

//Packedstructurerepresentsacollectionofvariables
//thatcanreferencedandpassedthroughportsasagroup
typedefstructpacked{
op_topcode;
operand_type_top_type;
data_top_a;
data_top_b;
}instruction_t;
endpackage:definitions_pkg
//`end_keywords

//`begin_keywords"1800-2012"http://useSystemVerilog-2012keywords
moduleinstruction_register
importdefinitions_pkg::*;//wildcardimportthepackage
(inputlogicclk,rstN,load_en,
inputdata_top_a,
inputdata_top_b,
inputoperand_type_top_type,
inputop_topcode,
inputlogic[4:0]write_pointer,
inputlogic[4:0]read_pointer,
outputinstruction_tiw
);
timeunit1ns;timeprecision1ns;

instruction_tiw_reg[0:31];//arrayofstructures

//writetotheregisterarray
always_ff@(posedgeclkornegedgerstN)//asyncreset
if(!rstN)begin//active-lowreset
foreach(iw_reg[i])
iw_reg[i]<=?'{opcode:ADD,default:0};?//?reset?values
???end?
???else?if?(load_en)?begin?
?????case?(op_type)
???????SIGNED:???iw_reg[write_pointer]?<=?
???????????????????'{opcode,op_type,op_a.s_data,op_b.s_data};
???????UNSIGNED:?iw_reg[write_pointer]?<=
???????????????????'{opcode,op_type,op_a.u_data,op_b.u_data};
?????endcase?
???end?
?//?read?from?the?register?array
?assign?iw?=?iw_reg[read_pointer];

endmodule:?instruction_register
//`end_keywords?

圖4-5顯示了綜合該示例的結(jié)果。說明了如何使用結(jié)構(gòu)體和聯(lián)合體、數(shù)組來建模大量設(shè)計(jì)功能，只需很少的代碼。示意圖右上角的矩形符號(hào)是綜合編譯器選擇報(bào)告的通用RAM的實(shí)例（在RTL模型中數(shù)組的存儲(chǔ)。）綜合編譯器將在綜合的最后一步將該通用RAM作為一個(gè)或多個(gè)同步存儲(chǔ)設(shè)備來實(shí)現(xiàn)，其中通用門級(jí)功能映射到特定的ASIC或FPGA設(shè)備。

圖4-5：示例4-8的綜合結(jié)果：帶結(jié)構(gòu)體的指令寄存器

附錄-TestBench

//`begin_keywords"1800-2012"
moduletest
importdefinitions_pkg::*;
(inputlogictest_clk,
outputlogicload_en,
outputlogicrstN,
outputdata_top_a,
outputdata_top_b,
outputop_topcode,
outputoperand_type_top_type,
outputlogic[4:0]write_pointer,
outputlogic[4:0]read_pointer,
inputinstruction_tiw
);

timeunit1ns;timeprecision1ns;

intseed=555;

initialbegin
$display("
Resetingtheinstructionregister...");
write_pointer=5'h00;//initializewritepointer
read_pointer=5'h1F;//initializereadpointer
load_en=1'b0;//initializeloadcontrolline
rstN<=?1'b0;????????????//?assert?rstN?(active?low)
????repeat?(2)?@(posedge?test_clk)?;??//?hold?in?reset?for?2?clk?cycles
????rstN???????????=?1'b1;????????????//?deassert?reset_n?(active?low)

????$display("
Writing?values?to?register?stack...");
????op_type?????=?SIGNED;
????op_a.s_data?=??3;
????op_b.s_data?=?-5;
????opcode??????=?ADD;
????load_en?????=?1'b1;??//?enable?writing?to?register
????@(posedge?test_clk)?;
????for?(int?i=0;?i<=2;?i++)?begin
??????write_pointer?=?i;
??????$display("Writing?to?register?location?%0d:?",?write_pointer);
??????$display("??opcode?=?%0d?(%s)",?opcode,?opcode.name);
??????$display("??op_type?=?%0d?(%s)",?op_type,?op_type.name);
??????if?(op_type?==?SIGNED)?begin
????????$display("??op_a.s_data?=?%0d",???op_a.s_data);
????????$display("??op_b.s_data?=?%0d
",?op_b.s_data);
??????end?else?begin
????????$display("??op_a.s_data?=?%0d",???op_a.u_data);
????????$display("??op_b.s_data?=?%0d
",?op_b.u_data);
??????end
??????@(negedge?test_clk)?;
??????op_a++;
??????op_b--;
??????opcode?=?op_t'(opcode?+?1);
??????op_type?=?op_type.next;
????end
????load_en?=?1'b0;??//?turn-off?writing?to?register

????//?read?back?and?display?same?three?register?locations
????$display("
Reading?back?the?same?register?locations?written...");
????for?(int?i=0;?i<=2;?i++)?begin
??????@(posedge?test_clk)?read_pointer?=?i;
??????@(negedge?test_clk)?;
??????$display("Read?from?register?location?%0d:?",?read_pointer);
??????$display("??iw.opcode?=?%0d?(%s)",?iw.opcode,?iw.opcode.name);
??????$display("??iw.op_type?=?%0d?(%s)",?iw.op_type,?iw.op_type.name);
??????if?(iw.op_type?==?SIGNED)?begin
????????$display("??iw.op_a.s_data?=?%0d",???iw.op_a.s_data);
????????$display("??iw.op_b.s_data?=?%0d
",?iw.op_b.s_data);
??????end?else?begin
????????$display("??iw.op_a.s_data?=?%0d",???iw.op_a.u_data);
????????$display("??iw.op_b.s_data?=?%0d
",?iw.op_b.u_data);
??????end
????end
????@(posedge?test_clk)?$finish;
??end
endmodule:?test

module?top;
??timeunit?1ns;?timeprecision?1ns;

??import?definitions_pkg::*;

??logic??????????clk;
??logic??????????test_clk;
??logic??????????rstN;
??logic??????????load_en;
??logic??????????reset_n;
??op_t???????????opcode;
??operand_type_t?op_type;
??data_t?????????op_a,?op_b;
??logic?[4:0]????write_pointer,?read_pointer;
??instruction_t??iw;

??test?????????????????test?(.*);
??instruction_register?dut??(.*);

??initial?begin
????clk?<=?0;
????forever?#5??clk?=?~clk;
??end

??initial?begin
????test_clk?<=0;
????//?offset?test_clk?edges?from?clk?to?prevent?races?between
????//?the?testbench?and?the?design
????#4?forever?begin
??????#2ns?test_clk?=?1'b1;
??????#8ns?test_clk?=?1'b0;
????end
??end
endmodule:?top
//`end_keywords

SystemVerilog-聯(lián)合體（union）

SystemVerilog-結(jié)構(gòu)體（二）

原文標(biāo)題：SystemVerilog-使用結(jié)構(gòu)體和聯(lián)合體的例子

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