SMP(對(duì)稱多處理)系統(tǒng)

SMP(對(duì)稱多處理)系統(tǒng)

Can SMP computing help predictive maintenance?

　　This question relates to last week’s question about smart instruments and predictive maintenance.

　　Symmetric multiprocessing (SMP) computer technology has been around for a few decades. Early SMP computers were used to create so-called “supercomputers” capable of tackling extreme compute-intensive problems by breaking the algorithm into separate modules that individual processor cores can operate on simultaneously.

　　There are two basic SMP strategies: pipeline and parallel processing. A pipeline is a set of operations performed sequentially on data packets visualized as streaming through the computer. Say the computation has been divided into 5 modules. A data packet comes into the first processor, which implements the first program module, then passes the result on to the second processor. The second processor implements the second module, while the first processor operates on the next data packet. Data packets continue streaming down the pipeline in assembly line fashion, each processor performing part of the analysis and passing the result on to the next processor. Like an assembly line, the pipeline takes raw data in at one end and pours finished analysis results out at the other.

　　Symmetric multiprocessing architecture has several processor cores connected to a common memory. The computation work can then be divided between the processor cores, improving system performance.

　　Parallel processing implements the complete algorithm on each processor. The system divides the data into chunks, with the number of chunks equaling the number of processors. Each processor does the complete analysis on its data chunk, and passes the result to the output.

　　More useful is a hybrid strategy, which combines parallel and pipeline processing. Some modules are performed in parallel, and some in series. The architecture can even change with time. For example, all of the processors may start off performing part of the analysis in series. When the whole data set has been analyzed, the processors may reorganize into a pipeline to further analyze the first-pass results. Then, maybe they reorganize again into a series-parallel arrangement for a third pass, and so forth.

　　These strategies were worked out in an era of single-core microprocessors. Today, we have multicore microcontrollers with as many as eight cores, and on-chip memory and I/O functions. The SMP strategy, however, is still the same.

　　Historically, SMP computing’s main purpose was to perform enormous compute-intensive projects in reasonable amounts of time. Early SMP applications included simulations of protein folding and global circulation climate models. Since multicore processors have become readily available, however, we have found other uses for them. For example, in a control application, we might run a real-time application on one, dedicated, core, while running other, less critical, applications, such as a human-machine interface, on another.

　　Predictive maintenance, on the other hand, is a system-level concept. The idea is to monitor selected variables that engineers believe to have predictive power. For example, a rise in a bearing’s temperature may warn of impending need for additional or replacement lubricant. Automatically monitoring such variables makes it possible for the system to tailor the maintenance program to the machinery’s actual needs, saving time, supplies, and replacement parts, and avoiding unplanned work stoppages. The alternative is scheduled maintenance, which generally provides more maintenance than necessary on average, but may miss extraordinary events.

　　Because machine conditions typically change over a time scale that is very long compared to computer processing speeds. Control loops can be closed on time scales varying from hours to months. Thus, SMP computing’s speed advantage is not typically needed. There may, however, be other advantages to applying SMP architecture to predictive maintenance applications. For example, it may be advantageous to isolate the predictive maintenance functions from real-time motion-control applications running on a multicore system. The SMP architecture, which gives all processors access to all data, would then allow the predictive maintenance system to monitor data collected for process-control purposes, and use it for maintenance scheduling purposes.

　　Speeds needed for effective control may vary over several orders of magnitude within one machine or system. Multiprocessor architectures allow control engineers to apply just the right computer speed for each control loop. Symmetric multiprocessor architecture may, however, not be the right architecture. In most complex control applications, an assymetric, asynchronous architecture with distributed memory would be a better fit.

　　Such an architecture arranges control loops in a hierarchy, with small embedded processors closing tight loops around individual degrees of freedom. The next level consists of control loops coordinating several degrees of freedom across a single machine to accomplish more complex tasks, such as moving a robot's end effector through a trajectory in three-space. A third level might coordinate the activities of multiple machines to integrate a process. Larger — and typically slower — loops coordinate wider activities, reaching up to the manufacturing execution system (MES), or even enterprise level.

　　Each level carries responsibility for its own activities; relying on data provided by, and implementing decisions via control signals sent to, the next lower level; and exchanging information with the next higher level. Information storage and processing needs generally are quite modest at lower levels, and increase at higher levels where decisions require pooling information from many sources and solving more complex analytical models.

　　Automated predictive maintenance would be implemented as a task at a relatively low level, where computation loads are relatively modest. SMP technology would be of relatively little value at that level.